 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semico nductor inc. all rights reserved. features ? integrated single-chip 10/100/1000 mbps ethernet switch ? 16 10/100 mbps autosensing, fast ethernet ports with rmii or serial interface (7ws). each port can independently use one of the two interfaces ? 2 gigabit ports with gmii, pcs and 10/100 interface options per port ? gigabit port supports hot swap in managed configuration. ? supports 8/16-bit cpu interface in managed mode ? serial interface in unmanaged mode ? supports two frame buffer memory domains with sram at 100 mhz ? supports memory size 2 mb, or 4 mb ? two sram domains (2 mb or 4 mb) are required ? applies centralized shared memory architecture ? up to 64 k mac addresses ? maximum throughput is 3.6 gbps non-blocking ? high performance packet forwarding (10.712 m packets per second) at full wire speed ? provides port based and id tagged vlan support (ieee 802.1q), up to 255 vlans ? supports ip multicast with igmp snooping ? supports spanning tree with cpu, on per port or per vlan basis ? packet filtering and port security ? static address filtering for source and/or destination mac ? static mac address not subject to aging ? secure mode freezes mac address learning. each port may independently use this mode. ? full duplex ethernet ieee 802.3x flow control ? backpressure flow control for half duplex ports ? supports ethernet multicasting and broadcasting and flooding control ? supports per-system option to enable flow control for best effort frames even on qos-enabled ports february 2004 ordering information zl50418/gkc 553-pin hsbga -40 c to +85 c zl50418 managed 16-port 10/100 m + 2-port 1 g ethernet switch data sheet figure 1 - zl50418 system block diagram fdb interface frame data buffer a sram (1 m / 2 m) led search engine mct link frame engine fcb management module 16 x 10 /100 rmii ports 0 - 15 vlan 1 mct frame data buffer b sram (1 m / 2 m) vlan 1 mct gmii/ port 0 pcs gmii/ port 1 pcs 16-bit parallel/ serial cpu
zl50418 data sheet 2 zarlink semiconductor inc. ? traffic classification ? 4 transmission priorities for fast ethernet ports with 2 dropping levels ? classification based on: - port based priority - vlan priority field in vlan tagged frame - ds/tos field in ip packet - udp/tcp logical ports: 8 hard-wired and 8 programmable ports, including one programmable range ? the precedence of the above classifications is programmable ? qos support ? supports ieee 802.1p/q quality of service with 4 tr ansmission priority queues with delay bounded, strict priority, and wfq service disciplines ? provides 2 levels of dropping precedence with wred mechanism ? user controls the wred thresholds ? buffer management: per class and per port buffer reservations ? port-based priority: vlan priority in a tagged frame ca n be overwritten by the priority of port vlan id ? 3 port trunking groups, one for the 2 gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group. or 8 groups for 10/100 ports with up to 2 10/100 ports per group ? load sharing among trunked ports can be based on s ource mac and/or destination mac. the gigabit trunking group has one more option, based on source port ? port mirroring to any two ports of 0-15 in managed mode or to a dedicated mirroring port in unmanaged mode ? full set of led signals provided by a serial interface, or 6 led signals dedicated to gigabit port status only (without serial interface) ? built-in mib statistics counters ? recognizes simple bandwidth management (sbm) and re source reservation potocol (rsvp) packets and forwards to cpu ? hardware auto-negotiation through serial management interface (mdio) for ethernet ports ? built-in reset logic triggered by system malfunction ? built-in self test for internal and external sram ?i 2 c eeprom for configuration ? 553 bga package zl50418 data sheet 3 zarlink semiconductor inc. description the zl50418 is a high density, low cost, high perform ance, non-blocking ethernet switch chip. a single chip provides 16 ports at 10/100 mbps, 2 ports at 1000 mbps and a cpu interface for managed and unmanaged switch applications. the gigabit ports can also support 10/100 m. the chip supports up to 64 k mac addresses and up to 255 port-based virtual lans (vlans). the centralized shared memory architecture permits a very high performance packet forwarding rate at up to 9.524 m packets per second at full wire speed. the chip is optimized to provide low-cost, high-performance workgroup switching. two frame buffer memory domains utilize cost-effective, high-performa nce synchronous sr am with aggregate bandwidth of 12.8 gbps to support full wire speed on all ports simultaneously. with delay bounded, strict priority, and/or wfq tran smission scheduling, and wred dropping schemes, the zl50418 provides powerful qos functions for various mu ltimedia and mission-critic al applications. the chip provides 4 transmission priorities (8 priorities per gigabit port) and 2 levels of dropping precedence. each packet is assigned a transmission priority and dropping precedence based on the vlan priority field in a vlan tagged frame, or the ds/tos field, and udp/tc p logical port fields in ip packets. the zl50418 recognizes a total of 16 udp/tcp logical ports, 8 hard-wired and 8 programmable (including one programmable range). the zl50418 supports 3 groups of port trunking/load sharin g. one group is dedicated to the two gigabit ports, and the other two groups to 10/100 ports where each 10/100 grou p can contain up to 4 ports. port trunking/load sharing can be used to group ports between interlinked swit ches to increase the effective network bandwidth. in half-duplex mode all ports support backpressure flow co ntrol to minimize the risk of losing data during long activity bursts. in full-duplex mode , ieee 802.3x flow control is provided. the zl50418 also s upports a per-system option to enable flow control for best effort frames, even on qos-enabled ports. the physical coding sublayer (pcs) is integrated on-chip to provide a direct 10-bit interface for connection to serdes chips. the pcs can be bypassed to provide a gmii interface. statistical information for snmp and the remote moni toring management information base (rmon mib) are collected independently for all ports. access to these statis tical counters/registers is pr ovided via the cpu interface. snmp management frames can be received and transmitte d via the cpu interface, creating a complete network management solution. the zl50418 is fabricated using 0.25 micron technology. inputs, however, are 3.3 v tolerant, and the outputs are capable of directly interfacing to lvttl levels. the zl 50418 is packaged in a 553-pin ball grid array package. zl50418 data sheet table of contents 4 zarlink semiconductor inc. 1.0 block functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 frame data buffer (fdb) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 gmii/pcs mac module (gmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3 physical coding sublayer (pcs) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.4 10/100 mac module (rmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.5 cpu interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 management module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.8 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.9 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.10 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 management and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 register configuration, frame transmission, and frame rece ption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.1 register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.2 rx/tx of standard ethernet frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.3 control frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.4 unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.3 data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.4 acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4.6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.1 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.5.2 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.0 zl50418 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 unicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 multicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 frame forwarding to and from cpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.0 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 detailed memory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 memory requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 search engine overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 basic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 search, learning, and aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.1 mac search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.2 learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.3 aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3.4 vlan table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 mac address filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 quality of service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.6 priority classification rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.7 port and tag based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8 port-based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.8.1 tag-based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.9 memory configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 zl50418 data sheet table of contents 5 zarlink semiconductor inc. 6.0 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 data forwarding summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 frame engine details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.1 fcb manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.2 rx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.3 rxdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2.4 txq manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4 txdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.0 quality of service and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1 model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2 four qos configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.3 delay bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.4 strict priority and best effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.5 weighted fair queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.6 shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.7 rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.8 wred drop threshold management support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.9 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.9.1 dropping when buffers are scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10 zl50418 flow control basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10.1 unicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.10.2 multicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.11 mapping to ietf diffserv classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.1 features and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 unicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.3 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.4 unmanaged trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.0 port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.1 port mirroring features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 setting registers for port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.0 tbi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 tbi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 11.0 gpsi (7ws) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.1 gpsi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 11.2 scan link and scan col interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.0 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.1 led interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.2 port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.3 led interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.0 hardware statistics counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.1 hardware statistics counters list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.2 eee 802.3 hub management (rfc 1516) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1.1 readableoctet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1.2 readableframe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.2.1.3 fcserrors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2.1.4 alignmenterrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2.1.5 frametoolongs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.2.1.6 shortevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 zl50418 data sheet table of contents 6 zarlink semiconductor inc. 13.2.1.7 runts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2.1.8 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2.1.9 lateevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2.1.10 verylongevents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2.1.11 dataratemisatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2.1.12 autopartitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2.1.13 totalerrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.3 ieee ? 802.1 bridge managemen t (rfc 1286) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.1.1 inframes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.1.2 outframes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.1.3 indiscards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.1.4 delayexceededdiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.3.1.5 mtuexceededdiscards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4 rmon ? ethernet statistic group (rfc 1757) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4.1 event counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4.1.1 drop events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4.1.2 octets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4.1.3 broadcastpkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4.1.4 multicastpkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.4.1.5 crcalignerrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4.1.6 undersizepkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4.1.7 oversizepkts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4.1.8 fragments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4.1.9 jabbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4.1.10 collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.4.1.11 packet count for different size groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.5 miscellaneous counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.0 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.1 zl50418 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14.2 directly accessed registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.2.1 index_reg0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.2.2 index_reg1 (only needed for 8-bit mo de) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 14.2.3 data_frame_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.2.4 control_frame_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.2.5 command&status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 14.2.6 interrupt register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14.2.7 control command frame buffer1 access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.2.8 control command frame buffer2 access register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.3 (group 0 address) mac ports group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.3.1 ecr1pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 14.3.2 ecr2pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14.3.3 ggcontrol ? extra giga port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14.4 (group 1 address) vlan group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.4.1 avtcl ? vlan type code register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 14.4.2 avtch ? vlan type code register hig h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14.4.3 pvmap00_0 ? port 00 configuration register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 14.4.4 pvmap00_1 ? port 00 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 14.4.5 pvmap00_3 ? port 00 configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 14.5 port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.5.1 pvmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 14.5.2 pvroute 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 zl50418 data sheet table of contents 7 zarlink semiconductor inc. 14.5.3 pvroute1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.5.4 pvroute2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.5.5 pvroute3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 14.5.6 pvroute4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.5.7 pvroute5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.5.8 pvroute6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.5.9 pvroute7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.6 (group 2 address) port trunking groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.6.1 trunk0_l ? trunk group 0 low (managed mode only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.6.2 trunk0_m ? trunk group 0 medium (managed mode only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 14.6.3 trunk0_mode? trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 14.6.4 trunk0_hash0 ? trunk group 0 hash result 0 dest ination port number . . . . . . . . . . . . . . . . . . 73 14.6.5 trunk0_hash1 ? trunk group 0 hash result 1 dest ination port number . . . . . . . . . . . . . . . . . . 74 14.6.6 trunk0_hash2 ? trunk group 0 hash result 2 dest ination port number . . . . . . . . . . . . . . . . . . 74 14.6.7 trunk0_hash3 ? trunk group 0 hash result 3 dest ination port number . . . . . . . . . . . . . . . . . . 74 14.6.8 trunk1_l ? trunk group 1 low (managed mode only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.6.9 trunk1_m ? trunk group 1 medium managed mode only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 14.6.10 trunk1_mode ? trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 14.6.11 trunk1_hash0 ? trunk gr oup 1 hash result 0 destin ation port number . . . . . . . . . . . . . . . . . 75 14.6.12 trunk1_hash1 ? trunk gr oup 1 hash result 1 destin ation port number . . . . . . . . . . . . . . . . . 75 14.6.13 trunk1_hash2 ? trunk gr oup 1 hash result 2 destin ation port number . . . . . . . . . . . . . . . . . 75 14.6.14 trunk1_hash3 ? trunk gr oup 1 hash result 3 destin ation port number . . . . . . . . . . . . . . . . . 75 14.6.15 trunk2_mode ? trunk group 2 mode (gigabit ports 1 and 2). . . . . . . . . . . . . . . . . . . . . . . . . 75 14.6.16 trunk2_hash0 ? trunk gr oup 2 hash result 0 destin ation port number . . . . . . . . . . . . . . . . . 76 14.6.17 trunk2_hash1 ? trunk gr oup 2 hash result 1 destin ation port number . . . . . . . . . . . . . . . . . 76 14.6.18 multicast hash registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 14.6.18.1 multicast_hash0-0 ? multicast hash result 0 mask byte 0 . . . . . . . . . . . . . . . . . . . . . . . . 76 14.6.18.2 multicast_hash0-1 ? multicast hash result 0 mask byte 1 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.3 multicast_hash0-3 ? multicast hash result 0 mask byte 3 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.4 multicast_hash1-0 ? multicast hash result 1 mask byte 0 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.5 multicast_hash1-1 ? multicast hash result 1 mask byte 1 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.6 multicast_hash1-3 ? multicast hash result 1 mask byte 3 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.7 multicast_hash2-0 ? multicast hash result 2 mask byte 0 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.8 multicast_hash2-1 ? multicast hash result 2 mask byte 1 . . . . . . . . . . . . . . . . . . . . . . . . 77 14.6.18.9 multicast_hash2-3 ? multicast hash result 2 mask byte 3 . . . . . . . . . . . . . . . . . . . . . . . . 78 14.6.18.10 multicast_hash3-0 ? multicast hash result 3 mask byte 0 . . . . . . . . . . . . . . . . . . . . . . . 78 14.6.18.11 multicast_hash3-1 ? multicast hash result 3 mask byte 1 . . . . . . . . . . . . . . . . . . . . . . . 78 14.6.18.12 multicast_hash3-3 ? multicast hash result 3 mask byte 3 . . . . . . . . . . . . . . . . . . . . . . . 78 14.7 (group 3 address) cpu port configuration group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.7.1 mac0 ? cpu mac address byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.7.2 mac1 ? cpu mac address byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14.7.3 mac2 ? cpu mac address byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.7.4 mac3 ? cpu mac address byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.7.5 mac4 ? cpu mac address byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.7.6 mac5 ? cpu mac address byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.7.7 int_mask0 ? interrupt mask 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 14.7.8 intp_mask0 ? interr upt mask for mac port 0,1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.7.9 intp_mask1 ? interr upt mask for mac port 2,3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.7.10 intp_mask2 ? interr upt mask for mac port 4,5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.7.11 intp_mask3 ? interr upt mask for mac port 6,7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.7.12 intp_mask4 ? interr upt mask for mac port 8,9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.7.13 intp_mask5 ? interr upt mask for mac port 10 ,11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 zl50418 data sheet table of contents 8 zarlink semiconductor inc. 14.7.14 intp_mask6 ? interr upt mask for mac port 12 ,13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 14.7.15 intp_mask7 ? interr upt mask for mac port 14 ,15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.7.16 intp_mask12 ? interrupt mask for ma c port g1,g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.7.17 rqs ? receive queue select cpu address:h323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.7.18 rqss ? receive queue status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 14.8 (group 4 address) search engine grou p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14.8.1 agetime_low ? mac address aging ti me low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14.8.2 agetime_high ?mac addre ss aging time high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 14.8.3 +scan ? scan control register (default 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 14.9 (group 5 address) buffer control/qos group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 14.9.1 fcbat ? fcb aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 14.9.2 qosc ? qos control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 14.9.3 fcr ? flooding control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.9.4 avpml ? vlan tag priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.9.5 avpmm ? vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.9.6 avpmh ? vlan priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.9.7 tospml ? tos priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.9.8 tospmm ? tos priority ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.9.9 tospmh ? tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.9.10 avdm ? vlan discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.9.11 tosdml ? tos discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 14.9.12 bmrc - broadcast/multicast rate cont rol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.9.13 ucc ? unicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.9.14 mcc ? multicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.9.15 pr100 ? port reservation for 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.9.16 prg ? port reservation for giga po rts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.9.17 sfcb ? share fcb size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.9.18 c2rs ? class 2 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.9.19 c3rs ? class 3 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.9.20 c4rs ? class 4 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.9.21 c5rs ? class 5 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.9.22 c6rs ? class 6 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.9.23 c7rs ? class 7 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.9.24 qoscn - classes byte limit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.9.25 classes byte limit set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.9.26 classes byte limit set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.9.27 classes byte limit set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.9.28 classes byte limit giga port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 14.9.29 classes byte limit giga port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.9.30 classes wfq credit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.9.31 classes wfq credit set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 14.9.32 classes wfq credit set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.9.33 classes wfq credit set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.9.34 classes wfq credit port g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 14.9.35 classes wfq credit port g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.9.36 class 6 shaper control port g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.9.37 class 6 shaper control port g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.9.38 rdrc0 ? wred rate control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.9.39 rdrc1 ? wred rate control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.9.40 user defined logical ports and well known ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.9.40.1 user_port0_(0~7) ? user define logical port (0 ~7). . . . . . . . . . . . . . . . . . . . . . . . . . . 97 14.9.40.2 user_port_[1:0]_priority - user define logi c port 1 and 0 priority . . . . . . . . . . . . . 97 zl50418 data sheet table of contents 9 zarlink semiconductor inc. 14.9.40.3 user_port_[3:2]_priority - user define logi c port 3 and 2 priority . . . . . . . . . . . . . 98 14.9.40.4 user_port_[5:4]_priority - user define logi c port 5 and 4 priority . . . . . . . . . . . . . 98 14.9.40.5 user_port_[7:6]_priority - user define logi c port 7 and 6 priority . . . . . . . . . . . . . 98 14.9.40.6 user_port_enable[7: 0] ? user define logic 7 to 0 port enables . . . . . . . . . . . . . . . 98 14.9.40.7 well_known_port[1:0] priority- well know n logic port 1 and 0 priority . . . . . . . 98 14.9.40.8 well_known_port[3:2] priority- well know n logic port 3 and 2 priority . . . . . . . 99 14.9.40.9 well_known_port [5:4] priority- well kn own logic port 5 and 4 priority . . . . . . 99 14.9.40.10 well_known_port [7:6] priority- well known logic port 7 and 6 priority . . . . . 99 14.9.40.11 well known_port_enable [7:0] ? well known logic 7 to 0 port enables. . . . . . 100 14.9.40.12 rlowl ? user define range low bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.9.40.13 rlowh ? user define range low bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.9.40.14 rhighl ? user define range high bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.9.40.15 rhighh ? user define range high bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.9.40.16 rpriority ? user define range priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 14.9.41 cpuqosc123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.10 (group 6 address) misc group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.10.1 mii_op0 ? mii register option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.10.2 mii_op1 ? mii register option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.10.3 fen ? feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.10.4 miic0 ? mii command register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.10.5 miic1 ? mii command register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.10.6 miic2 ? mii command register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.10.7 miic3 ? mii command register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.10.8 miid0 ? mii data register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.10.9 miid1 ? mii data register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.10.10 led mode ? led control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.10.11 device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 14.10.12 checksum - eeprom checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 14.11 (group 7 address) port mirroring group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 14.11.1 mirror1_src ? port mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 05 14.11.2 mirror1_dest ? port mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 14.11.3 mirror2_src ? port mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 14.11.4 mirror2_dest ? port mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 14.12 group f address) cpu access group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 14.12.1 gcr-global control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 14.12.2 dcr-device status and signature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 07 14.12.2.1 dcr1-giga port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 14.12.3 dpst ? device port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.12.4 dtst ? data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.12.5 pllcr - pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 14.12.6 lclk - la_clk delay from internal oe_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 14.12.7 oeclk - internal oe_clk delay from sclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.12.8 da ? da register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.13 tbi registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.13.1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.13.2 status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.13.3 advertisement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.13.4 link partner ability register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.13.5 expansion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.13.6 extended status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15.0 bga and ball signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 15.1 bga views (top views) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 zl50418 data sheet table of contents 10 zarlink semiconductor inc. 15.1.1 encapsulated view in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 15.1.2 encapsulated view in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 15.2 ball ? signal descriptions in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 15.2.1 ball signal descriptions in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 15.2.2 ball ? signal descriptions in unma naged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 15.3 ball ? signal name in unmanaged mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 15.4 ball ? signal name in managed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.5 ac/dc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.5.1 absolute maxi mum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.5.4 typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 15.5.5 typical cpu timing diagram for a cpu write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.5.6 typical cpu timing diagram for a cpu read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15.6 local frame buffer sbram memory inte rface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.6.1 local sbram memory interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 15.7 local switch database sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 15.7.1 local sbram memory interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 15.8 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15.8.1 reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 15.8.2 gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 15.8.3 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.8.4 scanlink scancol output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 15.8.5 mdio input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 15.8.6 i 2 c input setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 15.8.7 serial interface setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zl50418 data sheet list of figures 11 zarlink semiconductor inc. figure 1 - zl50418 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - overview of the cpu interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3 - data transfer format for i2c in terface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 4 - write command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 5 - read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6 - zl50418 sram interface block diagram (dmas for 10 /1000 ports only). . . . . . . . . . . . . . . . . . . . . . 21 figure 7 - memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8 - priority classification rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9 - memory configuration for: 2 banks, 1 layer, 2 mb to tal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10 - memory configuration for: 2 banks, 2 layer, 4 mb to tal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 11 - memory configuration for: 2 banks, 1 layer, 4 mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12 - behaviour of the wred logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13 - buffer partition scheme used to implement buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 14 - tbi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 15 - gpsi (7ws) mode connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 16 - scan link and scan collison status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17 - timing diagram of led interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 18 - typical reset & bootstrap timi ng diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 figure 19 - typical cpu timing diagram for a cpu write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 20 - typical cpu timing diagram for a cpu read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 figure 21 - local memory interface ? input setup and hold timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 22 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 figure 23 - local memory interface ? input setup and hold timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 24 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 25 - ac characteristics ? reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 26 - ac characteristics ? reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 27 - ac characteristics- gmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 28 - ac characteristics ? gigabit media independent interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 29 - gigabit tbi interfac e transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 30 - gigabit tbi interface receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 31 - ac characteristics- gmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 32 - ac characteristics ? gigabit media independent interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 33 - gigabit tbi interfac e transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 34 - gigabit tbi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 35 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 36 - scanlink scancol output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 37 - scanlink, scancol setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 38 - mdio input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 39 - mdio output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 figure 40 - i 2 c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 41 - i 2 c output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 figure 42 - serial interface setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 figure 43 - serial interface output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zl50418 data sheet list of tables 12 zarlink semiconductor inc. table 1 - memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2 - vlan index mapping table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 3 - vlan index port association table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 4 - port-based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5 - supported memory configurations (pipeline sbram mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6 - options for memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7 - two-dimensional world traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8 - four qos configurations for a 10/100 mbps port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9 - four qos configurations for a gigabit port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10 - mapping between zl50418 and ietf diffserv classes for gigabit ports . . . . . . . . . . . . . . . . . . . . . . . 40 table 11 - mapping between zl50418 and ietf diffserv classes fo r 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . 40 table 12 - zl50418 features enabling ietf diffserv standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13 - select via trunk0_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 14 - select via trunk1_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15 - unmanaged mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 16 - reset & bootstrap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 17 - write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 18 - read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 19 - ac characteristics ? local frame buffer sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . 151 table 20 - ac characteristics ? local switch database sbram me mory interface . . . . . . . . . . . . . . . . . . . . . . 152 table 21 - ac characteristics ? reduced me dia independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 table 22 - ac characteristics ? gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 table 23 - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 24 - input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 table 25 - ac characteristics ? gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 table 26 - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 27 - input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 table 28 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 table 29 - scanlink, scancol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 31 - i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 30 - mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 table 32 - serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 zl50418 data sheet 13 zarlink semiconductor inc. 1.0 block functionality 1.1 frame data buffer (fdb) interfaces the fdb interface supports pipelined synchronous burst sram (sbram) memory at 100 mhz. to ensure a non-blocking switch, two memory domains are required. each domain has a 64 bit wide memory bus. at 100 mhz, the aggregate memory bandwidth is 12.8 gbps, which is enough to support 16 10/100 mbps and 2 gigabit ports at full wire speed switching. the switching database is also locate d in the external sram; it is used for storing mac addresses and their physical port number. it is duplicated and stored in both memory domains. therefore, when the system updates the contents of the switching database it has to write the entry to both domains at the same time. 1.2 gmii/pcs mac module (gmac) the gmii/pcs media access control (m ac) module provides the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). the zl50418 gmac implements both gmii and mii interface, which offers a simple migration from 10/100 to 1 g. the gmac of the zl50418 meets the ieee 802.3z specification. it is able to operate in 10 m/100 m either half or full duplex mode with a back pressure /flow control mechanism or in 1 g full duplex mode with flow control mechanism. furtherm ore, it will automatically retransmit upon collision for up to 16 total transmissions. phy addresses for gmac are 01h and 02h. for fiber optics media, the zl50418 implements the physic al code sublayer (pcs) inte rface. the pcs includes an 8b10b encoder and decoder, auto-negotiation, and ten bit interface (tbi) 1.3 physical coding sublayer (pcs) interface for the zl50418, the 1000base-x pcs inte rface is designed internally and ma y be utilized in the absence of a gmii. the pcs incorporates all the functions required by the gmii to include encoding (decoding) 8b gmii data to (from) 8b/10b tbi format for phy communication and gener ating collision detect (col) signals for half-duplex mode. it also manages the auto negotiation process by informing the management entity that the phy is ready for communications. the on-chip tbi may be disabled if tbi exists within the gigabit phy. the tbi interface provides a uniform interface for all 1000 mbps phy implementations. the pcs comprises the pcs transmit, synchronization , pcs receive and auto negotiation processes for 1000base-x. the pcs transmit process sends the tbi signals txd [9 :0] to the physical medium and generates the gmii collision detect (col) signal based on whether a rec eption is occurring simult aneously with transmission. additionally, the transmit process generates an internal ?transmitting? flag and monitors auto negotiation to determine whether to transmit data or to reconfigure the link. the pcs synchronization process determines whet her or not the receive channel is operational. the pcs receive process generates rxd [7:0] on the gmii fr om the tbi data [9:0] and the internal ?receiving? flag for use by the transmit processes. the pcs auto negotiation process allows the zl50418 to exchange configuration information between two devices that share a link segment and to automatically configure the link for the appropriate speed of operation for both devices. zl50418 data sheet 14 zarlink semiconductor inc. 1.4 10/100 mac module (rmac) the 10/100 media access control module provides the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). th e zl50418 has two interfaces, rmii or serial (only for 10 m). the 10/100 mac of the zl50418 device meets the ieee 802.3 specification. it is able to operate in either half or full duplex mode with a back pr essure/flow control mechan ism. in addition, it w ill automatically retransmit upon collision for up to 16 total transmissions. the phy addresses for 16 10/1 00 mac are from 08h to 1fh. 1.5 cpu interface module one extra port is dedicated to the cpu via the cpu interface module. t he cpu interface utilizes a 16/8-bit bus in managed mode (bootstrap tstout6 makes the selection). it also supports a serial and an i 2 c interface, which provides an easy way to configure the system if unmanaged. 1.6 management module the cpu can send a control frame to access or configure the internal network management database. the management module decodes the control frame and executes the f unctions requested by the cpu. 1.7 frame engine the main function of the frame engine is to forward a fram e to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request which is sent to the search engine to resolve the destination port. the ar riving frame is moved to the fdb. after receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame?s priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.8 search engine the search engine resolves the frame?s destination port or ports according to the destination mac address (l2) or ip multicast address (ip multicast packet) by searching the database. it also performs mac learning, priority assignment and trunking functions. 1.9 led interface the led interface provides a serial inte rface for carrying 16+2 port status sign als. it can also provide direct status pins (6) for the two gigabit ports. 1.10 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contai ns the control information of the associated frame stored in the fdb, e.g., frame size, read/write pointer, transmission priority, etc. ? network management (nm) database - the nm database c ontains the information in the statistics counters and mib. ? mac address control table (mct) link table - the mct link table stores the linked list of mct entries that have collisions in the external mac table. note that the external mac table is located in the external ssram memory. zl50418 data sheet 15 zarlink semiconductor inc. 2.0 system configuration 2.1 management and configuration two modes are supported in the zl50418: managed and unmanaged. in managed mode, the zl50418 uses an 8 or 16 bit cpu interface very similar to the industry standard architecture (isa) specification. in unmanaged mode, the zl50418 has no cp u but can be configured by eeprom using an i 2 c interface at bootup or via a synchronous serial interface otherwise. 2.2 managed mode in managed mode, the zl50418 uses an 8 or 16 bit cpu interface very similar to the isa bus. the zl50418 cpu interface provides for easy and effective management of th e switching system. figure 1 provides an overview of the cpu interface. figure 2 - overview of the cpu interface 2.3 register configuration, frame transmission, and frame reception 2.3.1 register configuration the zl50418 has many programmable parameters covering such functions as qos weights, vlan control and port mirroring setup. in managed mode, the cpu interface prov ides an easy way of configuring these parameters. the parameters are contained in 8-bit configuration registers. the zl50418 allows indirect access to these registers, as follows: ? if operating in 8 bits-interface m ode, two ?index? registers (addresses 000 and 001) need to be written, to indicate the desired 8-bit register address. in 16-bit mode, only one register (address 000) needs to be written for the desired 16-bit register address. ? to indirectly configure the register addressed by the two index registers, a ?configure data? register (address 010) must be written with the desired 8-bit data. index reg 1 ( addr = 001 ) index reg 0 ( addr = 000 ) config data reg (addr = 010) frame data reg ( addr = 011 ) control block reg cpu frame receive fifo cpu frame transmit fifo control command frame receive fifo control command frame transmit fifo 1 and 2 internal configue registers synchronous serial interface 8/16 bit internal data bus 8/16 bit internal data bus 8 bit internal data bus 16 bit internal address bus zl50418 data sheet 16 zarlink semiconductor inc. ? similarly, to read the value in the register addressed by the two index registers, the ?configure data? register can now simply be read. in summary, access to the many internal registers is carrie d out simply by directly accessing only three registers ? two registers to indicate the address of the desired paramete r and one register to read or write a value. of course, because there is only one bus master, there can nev er be any conflict between reading and writing the configuration registers. 2.3.2 rx/tx of standard ethernet frames the cpu interface is also responsible fo r receiving and transmitting standard ethernet frames to and from the cpu. to transmit a frame from the cpu ? the cpu writes a ?data frame? register (address 011) with the data it wants to transmit (minimum 64 bytes). after writing all the data, it then writes the frame size, destination port number, and frame status. ? the zl50418 forwards the ethernet frame to the desir ed destination port, no longer distinguishing the fact that the frame originated from the cpu. to receive a frame into the cpu ? the cpu receives an interrupt when an et hernet frame is available to be received. ? frame information arrives first in the data frame register. this includes source port number, frame size and vlan tag. ? the actual data follows the frame information. the cpu uses the frame size information to read the frame out. in summary, receiving and transmitting frames to and from the cpu is a simple process that uses one direct access register only. 2.3.3 control frames in addition to standard ethernet frames described in the preceding section, the cpu is also called upon to handle special ?control frames,? generated by the zl50418 and se nt to the cpu. these proprietary frames are related to such tasks as statistics collection, mac address learning, ag ing, etc. all control frames are up to 40 bytes long. transmitting and receiving these frames is similar to tr ansmitting and receiving ethern et frames, except that the register accessed is the ?control frame data? register (address 111). specifically, there are eight types of control fram es generated by the cpu and sent to the zl50418: ? memory read request ? memory write request ? learn mac address ? delete mac address ? search mac address ? learn ip multicast address ? delete ip multicast address ? search ip multicast address note : memory read and write requests by the cpu may incl ude vlan table, spanning tree, statistic counters and similar updates. in addition, there are nine types of control fram es generated by the zl50418 and sent to the cpu: ? interrupt cpu when statistics counter rolls over ? response to memory read request from cpu zl50418 data sheet 17 zarlink semiconductor inc. ? learn mac address ? delete mac address ? delete ip multicast address ? new vlan port ? age out vlan port ? response to search mac address request from cpu ? response to search ip multicast address request from cpu the format of the control frame is described in the processor interface application note. 2.3.4 unmanaged mode in unmanaged mode, the zl50418 can be configur ed by eeprom (24c02 or compatible) via an i 2 c interface at boot time or via a synchronous se rial interface during operation. 2.4 i 2 c interface the i 2 c interface uses two bus lines, a serial data line (sda) and a serial clock line (scl). the scl line carries the control signals that facilitate the transfer of information fr om eeprom to the switch. data transfer is 8-bit serial and bidirectional, at 50 kbps. data transfer is performed between master and slave ic using a request / acknowledgment style of protocol. the master ic gener ates the timing signals an d terminates data transfer. figure 3 depicts the data transfer format. 2.4.1 start condition generated by the master (in our case, the zl50418). the bus is considered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a high-to-low transition of the sda line. other than in the start condition (and stop condition) , the data on the sda line must be stable during the high period of scl. the high or low state of sda can only change when scl is low. in addition, when the i 2 c bus is free both lines are high. 2.4.2 address the first byte after the start conditio n determines which slave the master will select. the slave in our case is the eeprom. the first seven bits of the first data byte make up the slave address. 2.4.3 data direction the eighth bit in the first byte after the start conditio n determines the direction (r /w) of the message. a master transmitter sets this bit to w; a ma ster receiver sets this bit to r. 2.4.4 acknowledgment like all clock pulses, the acknowledgment-related clock pu lse is generated by the master. however, the transmitter releases the sda line (high) during the acknowledgment cl ock pulse. furthermore, the receiver must pull down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte, then the master generates a stop condition and aborts the transfer. start slave address rw ack data1 (8bits) ack data 2 ack data m ack stop figure 3 - data transfer format for i 2 c interface zl50418 data sheet 18 zarlink semiconductor inc. if a master receiver does not acknowledge after any byte, th en the slave transmitter must release the sda line to let the master generate the stop condition. 2.4.5 data after the first byte containing the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb first. 2.4.6 stop condition generated by the master. the bus is considered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. the i 2 c interface serves the function of configuring the zl50 418 at boot time. the master is the zl50418, and the slave is the eeprom memory. 2.5 synchronous serial interface the synchronous serial interface serves the function of configuring the zl504 18 not at boot time but via a pc. the pc serves as master and the zl50418 serves as slave. the protocol for the synchronous serial interface is nearly identical to the i 2 c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged zl50418 uses a synchronous serial interfac e to program the internal registers. to reduce the number of signals required the register address, command and data are shifted in serially through the d0 pin. strobe- pin is used as the shift clock. autofd- pin is used as data return path. each command consists of four parts. ? start pulse ? register address ? read or write command ? data to be written or read back any command can be aborted in the middle by sending an abort pulse to the zl50418. a start command is detected when d0 is sampled high when strobe- rise and d0 is sampled low when strobe- fall. an abort command is detected when d0 is sampled low when strobe- rise and d0 is sampled high when strobe- fall. zl50418 data sheet 19 zarlink semiconductor inc. 2.5.1 write command figure 4 - write command 2.5.2 read command figure 5 - read command all registers in zl50418 can be modified th rough this synchronous serial interface. 3.0 zl50418 data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). an fcb handle will always be available becaus e of advance buffer reservations. the memory (sram) interface is two 64-bit buses, co nnected to two sram banks, a and b. the receive dma (rxdma) is responsible for multiplexing the data and the address. on a port ?s ?turn,? the rxdma will move 8 bytes (or up to the end-of-frame) from the port?s associated rxfifo into memory (fra me data buffer, or fdb). once an entire frame has been moved to the fdb and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination mac addresses of the frame. the search engi ne places a switch respon se in the switch response queue of the frame engine when done. among other information the search engine will have resolved the destination port of the fram e and will have determined th at the frame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. but first, the txq manager has to decide whether or not to drop the frame, based on global fdb reservations and usage, as well as txq occupancy strobe- d0 a0 a2 ... a9 a10 a11 a1 w d0 d1 d2 d3 d4 d5 d6 d7 start address command data 2 extra clocks after last transfer strobe- d0 autofd- a0 a1 a2 ... a9 a10 a11 r d0 d1 d2 d3 d4 d5 d6 d7 start address command data zl50418 data sheet 20 zarlink semiconductor inc. at the destination. if the frame is not dropped then the txq manager links the frame?s fcb to the correct per-port-per-class txq. unicast txq?s ar e linked lists of transmission jobs, re presented by their associated frames? fcb?s. there is one linked list for each transmission class fo r each port. there are 4 transmission classes for each of the 16 10/ 100 ports, and 8 classes for each of th e two gigabit ports ? a total of 112 unicast queues. the txq manager is responsible for scheduling transmissi on among the queues representing different classes for a port. when the port control module det ermines that there is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues for that port, using a zarlink semiconductor scheduling algorithm. the transmission dma (txdma) is responsible for multiplexing the data and the address. on a port?s turn, the txdma will move 8 bytes (or up to the eo f) from memory into the port?s asso ciated txfifo. afte r reading the eof, the port control requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 3.2 multicast data frame forwarding after receiving the swit ch response, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utiliz ation and reservations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet?s destinations. if so, then the frame is dropped at so me destinations but not others, and the fcb is not released. if the frame is not dropped at a partic ular destination port, then the txq manager formats an entry in the multicast queue for that port and class. mult icast queues are physical queues (unlik e the linked lists for unicast frames). there are 2 multicast queues for each of the 16 10/100 port s. the queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. t here are 4 multicast queues for each of the two gigabit ports. the size of the queues are: 32 entries (higher pr iority queue), 32 entries, 32 entries and 64 entries (lower priority queue). there is one multicast queue for every two priority classes. for the 10/100 ports to map the 8 transmit priorities into 2 multicast queues, the 2 lsb ar e discarded. for the gigabit ports to map the 8 transmit priorities into 4 multicast queues, the lsb are discarded. during scheduling, the txq manager treats the unicast queue and the multicast queue of the same class as one logical queue. the older head of line of the two queues is forwarded first. the port control requests a fcb release only after the eof for the multicast frame has been read by all ports to which the frame is destined. 3.3 frame forwarding to and from cpu frame forwarding from the cpu port to a regular transmi ssion port is nearly the same as forwarding between transmission ports. the only difference is that the physical destination port must be indicated in addition to the destination mac address. frame forwarding to the cpu port is nearly the same as forwarding to a regular transmission port. the only difference is in frame scheduling. instead of using the patent-pending zarlink semic onductor scheduling algorithms, scheduling for the cpu port is simply bas ed on strict priority. that is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue. there are four output queues to the cpu and one receive queue. zl50418 data sheet 21 zarlink semiconductor inc. 4.0 memory interface 4.1 overview the zl50418 provides two 64-bit-wide sram banks, sram bank a and sram bank b with a 64-bit bus connected to each. each dma can read and write from both bank a and bank b. the following figure provides an overview of the zl50418 sram banks. figure 6 - zl50418 sram interface block diagram (dmas for 10/1000 ports only) 4.2 detailed memory information because the bus for each bank is 64 bits wide, frames ar e broken into 8-byte granules, written to and read from memory. the first 8-byte granule gets written to bank a, the second 8-byte granule gets written to bank b, and so on in alternating fashion. when reading frames from memory, the same procedure is followed, first from a, then from b, and so on. the reading and writing from alternating memory banks can be performed with minimal waste of memory bandwidth. what?s the worst case? for any speed port , in the worst case, a 1-byte-long eof granule gets written to bank a. this means that a 7-byte segment of bank a bandwidth is idle, and furthermore, the next 8-byte segment of bank b bandwidth is idle, because the first 8 bytes of the next frame will be written to bank a, not b. this scenario results in a maximum 15 bytes of waste per frame, whic h is always acceptable because the interframe gap is 20 bytes. the cpu management port gets treated like any other port, reading and writing to alternating memory banks starting with bank a. the vlan index mapping table a nd mac address table are duplicated in bank a and b. when the cpu writes an entry to the vlan index mapping table it has to write the same data in bank a and bank b. search engine data is written to both banks in para llel. in this way, a search engine read operation can be performed by either bank at any time without a problem. sram bank a txdma 0-7 txdma 8-15 rxdma 0-7 rxdma 8-15 sram bank b zl50418 data sheet 22 zarlink semiconductor inc. 4.3 memory requirements to speed up searching and decrease memory latency, t he external mac address datab ase is duplicated in both memory banks. to support 64 k mac address, 4 mb memo ry is required. when vlan support is enabled, 512 entries of the mac address table are used for stor ing the vlan id at vlan index mapping table. up to 2 k ethernet frame buffers are supported and th ey will use 3 mb of memory. each frame uses 1536 bytes. the maximum system memory requirement is 4 mb. if less memory is desired, the configuration can scale down. memory configuration memory map figure 7 - memory map bank a bank b tag based vlan frame buffer max mac address 1m 1m disable 1k 32k 1m 1m enable 1k 31.5k 2m 2m disable 2k 64k 2m 2m enable 2k 63.5k table 1 - memory configuration 1m bank a 0.75 m 0.25 m tag based vlan disable 1 m bank b 0.75 m 0.25 m 1m bank a 0.75 m 0.25 m -4 k 1 m bank b 0.75 m 0.25 m- 4k 4k tag based vlan enable 2 m bank a 1.5 m 0.5 m 2 m bank b 1.5 m 0.5 m 2 m bank a 1.5 m 0.5 m -4 k 2 m bank b 1.5 m 0.5 m- 4k 4k tag based vlan enable frame data buffer (fdr) area mac address control table (mct) area vlan table area zl50418 data sheet 23 zarlink semiconductor inc. 5.0 search engine 5.1 search engine overview the zl50418 search engine is optimized for high th roughput searching, with en hanced features to support ? up to 64 k mac addresses ? up to 255 vlan and ip multicast groups ? 3 groups of port trunking (1 for the two gigabit ports, and 2 others) ? traffic classification into 4 (or 8 for gigabit) transmission priorities, and 2 drop precedence levels ? packet filtering ?security ?ip multicast ? flooding, broadcast, multicast storm control ? mac address learning and aging 5.2 basic flow shortly after a frame enters the zl50418 and is written to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the search engine. the switch request consists of th e first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. when the search engine is done, it writes to the switch response queue and the fr ame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted are the source and destination mac addres ses, the transmission and discard priorities, whether the frame is unicast or multic ast and vlan id. requests are sent to the external sram to locate the associated entrie s in the external hash table. when all the information has been collected from extern al sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other t han the first of each linked list are maintained internal to the chip. if the desired mac address is still not found, then the result is ei ther learning (s ource mac address unknown) or flooding (desti nation mac address unknown). in addition, vlan information is used to select the correct set of destination ports for the frame (for multicast) or to verify that the frame?s destination port is associated with the vlan (for unicast). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the frame be tran smitted? this is easily com puted using a hash of the source and destination mac addresses. as stated earlier, when all the information is compiled, the switch res ponse is generated. the search engine also interacts with the cpu with regard to learning and aging. zl50418 data sheet 24 zarlink semiconductor inc. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source mac address and destination mac address (or destination ip address for ip multicast) searching. as we indicated earlier, if a match is not found, then the next entry in the linked list must be examined and so on until a match is found or the end of the list is reached. in tag based vlan mode, if the frame is unicast and the de stination port is not a member of the correct vlan, then the frame is dropped; otherwise the frame is forwarded. if t he frame is multicast, this sa me table is used to indicate all the ports to which the frame will be forwarded. moreover, if po rt trunking is enabled, this block selects the destination port (among those in the trunk group). in port based vlan mode, a bitmap is used to determi ne whether the frame should be forwarded to the outgoing port. the main difference in this mode is that the bitmap is not dynamic. ports cannot enter and exit groups because of real-time learning made by a cpu. the mac search block is also responsible for updati ng the source mac address timestamp and the vlan port association timestamp, used for aging. 5.3.2 learning the learning module learns new mac addresses and perform s port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. when cpu reporting is enabled, lear ning and port change will be perform ed when the cpu re quest queue has room, and a memory slot is available, and a ?learn mac ad dress? message is sent to the cpu. when fast learning mode is enabled, learning and port change will be perfor med when memory slot is av ailable and a latter ?learn mac address? message is sent to the cpu when cpu queue has room. when cpu reporting is disabled, learning and port change will be pe rformed based on memory slot availability only. in tag based vlan mode, if the source port is not a me mber of a classified vlan, a ?new vlan port? message is sent to the cpu. the cpu can decide whether or not the source port can be added to the vlan. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a programmable ?age out? time interval. as we indicated earlier, the search module updates the source mac addre ss and vlan port association timestamps for each frame it processes. when an entry is ready to be aged, the en try is removed from the table, and a ?delete mac address? message is sent to inform the cpu. supported mac entry types are: dynamic, static, source filter, destination filter, ip multicast, source and destination filter, and secure mac address. only dynamic entries can be aged; all others are static. the mac entry type is stored in the ?status? field of the mct data structure. 5.3.4 vlan table the table below provides a mapping from vlan id to vlan index. it is maintained by system software and is checked by the hardware search engine for every incoming frame. this table has 4 k entries and is stored in external sram. it is organized as 512 8 entries (total of 4 k vlan indexes) as shown. each vlan index is 8 bits. zl50418 data sheet 25 zarlink semiconductor inc. each vix represents the mapping result from the asso ciated vlan id (vlanid = 0x004 is mapped to vix4). unused vlan id?s have their corresponding vix prog rammed to hexadecimal 00. used vlan id?s have their corresponding vix programmed to hexadecimal 01 through ff . in other words, 255 vlan?s are supported. the vix value is a pointer to the entries in the vlan index port association table (internal memory). the vlan index port association table is used by both soft ware and hardware. it contains 256 entries. each entry has 19 fields, such that each field represent s the port status of that particular vlan. table 3 - vlan index port association table each entry has 64 bits. each port has a vlan status field with the following two bits values: - 00: port not a member of vlan - 01: port is a member of vlan, and is subject to aging (do not use. used by the aging module) - 10: port is a member of vlan, and is subject to aging - 11: port is a member of vlan , and is not subject to aging note: the vlan aging time is controlled by register 402h. 5.4 mac address filtering the zl50418's implementation of intelligent traffic swit ching provides filters for source and destination mac addresses. this feature filt ers unnecessary traffic, th ereby providing intelligent c ontrol over traffic flows and broadcast traffic. mac address filtering allows the zl50418 to block an incomi ng packet to an interface when it sees a specified mac address in either the source address or destination address of the incoming packet. for example, if your network is congested because of high utilization fr om a mac address, you can filter all traffic transmitted from that address and restore network flow, while you troubleshoot the problem. vix7 vix6 vix5 vix4 vix3 vix2 vix1 vix0 ???????? ???????? vix4095 vix4094 vix4093 vix4092 vix4091 vix4090 vix4089 vix4088 table 2 - vlan index mapping table port not used g1 g0 cpu p15 p14 ?? p3 p2 p1 p0 bit 63 to 54 53 52 51 50 49 48 31 30 29 28 7 6 5 4 3 2 1 0 e n t r i e s 0 1 : : 255 zl50418 data sheet 26 zarlink semiconductor inc. 5.5 quality of service quality of service (qos) refers to the ability of a network to provide better se rvice to selected network traffic over various technologies. primary goals of qos include dedi cated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic), and improved loss characteristics. traditional ethernet networks have had no prioritization of traffic. without a protocol to prioritize or differentiate traffic, a service level known as ?best effort? attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. in a congested network or when a low-performance switch/router is overloaded, ?best effo rt? becomes unsuitable for delay-sensit ive traffic and mission-critical data transmission. the advent of qos for packet-base d systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing ethernet network. it al so alleviates the congestion issues that have previously plagued such ?best effort? networking systems. qos pr ovides ethernet networks with the breakthrough technology to prioritize traffic and ens ure that a certain transmission will have a guaranteed mi nimum amount of bandwidth. extensive core qos mechanisms are built into the zl50418 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue(wfq) scheduling at the egress port. in the zl50418, qos-based policies sort traffic into a small number of classes and mark the packets accordingly. the qos identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. for example, the overall se rvice given to frames and packets in the premium class will be better than that given to the stan dard class; the premium cl ass is expected to experience lower loss rate or delay. the zl50418 supports the following qos techniques: ? in a port-based setup, any station connected to the sa me physical port of the switch will have the same transmit priority. ? in a tag-based setup, a 3-bit field in the vlan tag prov ides the priority of the packet. this priority can be mapped to different queues in the switch to provide qos. ? in a tos/ds-based set up, tos stands for ?type of se rvice? that may include ?minimize delay,? ?maximize throughput? or ?maximize reliability.? network nodes may select routing paths or forwarding behaviours that are suitably engineered to satisfy the service request. ? in a logical port-based set up, a logical port provides the application information of the packet. certain applications are more sensitive to delays than others; us ing logical ports to classify packets can help speed up delay sensitive applications such as voip. zl50418 data sheet 27 zarlink semiconductor inc. 5.6 priority classification rule figure 8 on page 27 shows the zl50418 priority classification rule. figure 8 - priority classification rule 5.7 port and tag based vlan the zl50418 supports tw o models for determining and controlling how a packet gets assigned to a vlan: port priority and tag -based vlan. 5.8 port-based vlan an administrator can use the pvmap regi sters to configure the zl50418 for po rt-based vlan (see ?registration definition? on page 42). for example, ports 1-3 might be assigned to the marketing vlan, ports 4-6 to the engineering vlan, and ports 7-9 to the administrative vlan. the zl50418 determines the vlan membership of each packet by noting the port on which it arrives. from there, the zl50418 determines which outgoing port(s) is/are eligible to tr ansmit each packet, or whether the packet should be discarded. gigabit port 0 and 1 are denoted as port 25 and 26 respectively. destination port numbers bit map port registers 26 ? 2 1 0 register for port #0 pvmap00_0[7:0] to pvmap00_3[2:0] 0110 register for port #1 pvmap01_0[7:0] to pvmap01_3[2:0] 0101 register for port #2 pvmap02_0[7:0] to pvmap02_3[2:0] 0000 ? register for port #26 pvmap26_0[7:0] to pvmap26_3[2:0] 0000 table 4 - port-based vlan fix port priority ? yes yes yes yes yes yes no no no no no use tos use logical port use default port settings use vlan priority use default port settings tos precedence over vlan? vlan tag ? ip frame ? ip (fcr register, bit 7) no use logical port zl50418 data sheet 28 zarlink semiconductor inc. for example, in the above table a 1 denot es that an outgoing port is eligible to receive a packet from an incoming port. a 0 (zero) denotes that an outgoing port is no t eligible to receive a packet from an incoming port. in this example: ? data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. ? data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2. ? data packets received at port #2 are not eligible to be sent to ports 0 and 1. 5.8.1 tag-based vlan the zl50418 supports the i eee 802.1q specificat ion for ?tagging? frames. the specific ation defines a way to coordinate vlans across multiple switches . in the specification, an additional 4-octet header (or ?tag?) is inserted in a frame after the source mac address and before the frame type. 12 bits of the tag are used to define the vlan id. packets are then switched through the network with each zl50418 simply swapping the incoming tag for an appropriate forwarding tag rather than processing each packet's contents to determine the path. this approach minimizes the processing needed once the packet enters th e tag-switched network. in addition, coordinating vlan ids across multiple switches enables vl ans to extend to multiple switches. up to 255 vlans are supported in the zl50418. the 4 k vlans specified in the ieee 802.1q are mapped to 255 vlan indexes. the mapping is made by the vlan index mapping table. based on the vlan index (vixn), the source and destination port membership is checked against the content in the vlan index port association table. if the destination port is a member of the vlan, the packet is forwarded; otherwis e it is discarded. if the source port is not a member, a ?new vlan port? message is sent to the cp u. a filter can be applied to discard the packet if the source port is not a member of the vlan. 5.9 memory configurations the zl50418 supports the following memory configurations. pipeline sbram modes support 1 m and 2 m per bank configurations. for detail connection information, please reference the memory application note. configuration 1 m per bank (bootstrap pin tstout7 = open) 2 m per bank (bootstrap pin tstout7 = pull down) connections single layer (bootstrap pin tstout13 = open) two 128 k x 32 sram/bank or one 128 k x 64 sram/bank two 256 k x 32 sram/bank connect 0e# and we# double layer (bootstrap pin tstout13 = pull down) na four 128 k x 32 sram/bank or two 128 k x 64 sram/bank connect 0e0# and we0# connect 0e1# and we1# table 5 - supported memory configurations (pipeline sbram mode) zl50418 data sheet 29 zarlink semiconductor inc. figure 9 - memory configuration for : 2 banks, 1 layer, 2 mb total only bank a bank a and bank b 1m (sram) 2m (sram) 1m/bank (sram) 2m/bank (sram) zl50415 x x zl50416 x x zl50417 x x zl50418 x x table 6 - options for memory configuration a ddress la_a[19:3] sram memory 128 k 32 bits memory 128 k 32 bits data la_d[63:32] data la_d[31:0] a ddress lb_a[19:3] sram memory 128 k 32 bits memory 128 k 32 bits data lb_d[63:32] data lb_d[31:0] bank a (1m one layer) bank b (1m one layer) bootstraps: tstout7 = open, tstout13 = open, tstout4 = open zl50418 data sheet 30 zarlink semiconductor inc. figure 10 - memory configuration for: 2 banks, 2 layer, 4 mb total figure 11 - memory configuration for: 2 banks, 1 layer, 4 mb bank a (2m two layers) bank b (2m two layers) sram memory 128 k 32 bits sram memory 128 k 32 bits data lb_d[63:32] data lb_d[31:0] a ddress lb_a[19:3] sram memory 128 k 32 bits sram memory 128 k 32 bits sram memory 128 k 32 bits sram memory 128 k 32 bits data la_d[63:32] data la_d[31:0] a ddress la_a[19:3] sram memory 128 k 32 bits sram memory 128 k 32 bits bootstraps: tstout7 = pull down, tstout13 = pull down, tstout4 = open a ddress la_a[20:3] sram memory 256 k 32 bits memory 256 k 32 bits data la_d[63:32] data la_d[31:0] a ddress lb_a[20:3] sram memory 256 k 32 bits memory 256 k 32 bits data lb_d[63:32] data lb_d[31:0] bank a (2m one layer) bank b (2m one layer) bootstraps: tstout7 = pull down, tstout13 = open, tstout4 = open zl50418 data sheet 31 zarlink semiconductor inc. 6.0 frame engine 6.1 data forwarding summary when a frame enters the de vice at the rxmac, the rxdma will move th e data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjun ction with the scheme for the sram interface. a switch request is sent to the search engine. the search engine processes the switch request. a switch response is sent back to the frame engine and indicates whether the frame is unicast or multicast and its destination port or ports. a vlan table lookup is performed as well. a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling reque st, the device will format an entry in t he appropriate transm ission scheduling queue (txsch q) or queues. there are 4 txsch q for each 10/100 port (and 8 per gigabit port), one for each priority. creation of a queue entry either involves linking a new job to the appropriate linked list if unicast or adding an entry to a physical queue if multicast. when the port is ready to accept the next frame, the txq manager will get the head-of -line (hol) en try of one of the txsch qs, according to the transmission scheduling al gorithm (so as to ensure per-class quality of service). the unicast linked list and the multicast queue for the same port-class pa ir are treated as one logical queue. the older hol between the two queues goes first. for 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. for gigabit port s multicast queue 0 is associated with unicast queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast queue 3 with unicast queue 6. the txdma will pull frame data from the memory and forward it granule-by-g ranule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of each of the modules of the zl50418 frame engine. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming frames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enforcing buffe r reservations and limits. the default values can be determined by referring to chapter 7. in addition, the fc b manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct txsch q. the buf fer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register fcbat. 6.2.2 rx interface the rx interface is mainly responsi ble for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an end of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. zl50418 data sheet 32 zarlink semiconductor inc. 6.2.4 txq manager first, the txq manager checks the per- class queue status and gl obal reserved re source situation and using this information makes the frame dropping decision after receiving a switch response. if the decision is not to drop, the txq manager requests that the fcb manager link the unicast frame?s fcb to the correct per-port-per-class txq. if multicast, the txq manager writes to the multicast queue for that port and class. the txq manager can also trigger source port flow control for the incoming frame?s so urce if that port is flow control enabled. second, the txq manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read addres s for the frame currently being transmitted. it also writes start of frame information and an end of frame flag to th e mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control and arbitrates among buffer release requests from the port control modules. 7.0 quality of se rvice and flow control 7.1 model quality of service is an all-encompassi ng term for which different people have different interpretations. in general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. we also assume that the incoming traffic is not policed or sh aped. furthermore, we assume that the network manager knows his applications, such as voice, file transfer or web browsing and their relative importance. the manager can then subdivide the applications into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per clas s. sometimes it may even reflect an estimate of the traffic mix offered to the switch. as an added bonus, although we do not assume an ything about the arrival pattern, if the incoming traffic is policed or shaped we may be able to provide ad ditional assurances about ou r switch?s performance. table 8 shows examples of qos applications with three transm ission priorities, but best effort (p0) traffic may form a fourth class with no bandwidth or latency assurances . gigabit ports actually hav e eight total transmission priorities. goals total assured bandwidth (user defined) low drop probability (low-drop) high drop probability (high-drop) highest transmission priority, p3 50 mbps apps: phone calls, circuit emulation. latency: < 1 ms. drop: no drop if p3 not oversubscribed. apps: training video. latency: < 1 ms. drop: no drop if p3 not oversubscribed; first p3 to drop otherwise. table 7 - two-dimensional world traffic zl50418 data sheet 33 zarlink semiconductor inc. a class is capable of offering traffic that exceeds the co ntracted bandwidth. a well-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast , a misbehaving class offers traffic that exceeds the agreed-upon rate. a misbehaving class is formed from an aggregation of misbehaving mi croflows. to achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. howe ver, such leniency must not degrade the quality of service (qos) received by well-behaved classes. as table 8 illustrates, the six traffic types may each have their own distinct properties and applications. as shown, classes may receive bandwidth assurances or latency bounds. in the ta ble, p3, the highest transmission class, requires that all frames be transmitted within 1 ms, and re ceives 50% of the 100 mbps of bandwidth at that port. best-effort (p0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. it is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, then it goes first. in the zl50418, each 10/100 mbps port will support four total classes, and each 1000 mbps port will support ei ght classes. we will discuss the various modes of scheduling these classes in the next section. in addition, each transmission class has two subclasses, high-drop and low-drop. well-behaved users should rarely lose packets. but poorly behaved users ? users who send frames at too high a rate ? will encounte r frame loss, and the first to be discarded will be high-drop. of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. table 8 shows that different types of applications may be pl aced in different boxes in the traffic table. for example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas voip fits into the category of low-loss , low-latency traffic. 7.2 four qos configurations there are four basic pieces to qos scheduling in the zl 50418: strict priority (sp), delay bound, weighted fair queuing (wfq), and best effort (be). using these four piec es, there are four different modes of operation, as shown in the tables below. for 10/100 mbps ports, the following registers select these modes: middle transmission priority, p2 37.5 mbps apps: interactive apps, web business. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed. apps: non-critical interactive apps. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed; firstp2 to drop otherwise. low transmission priority, p1 12.5 mbps apps: emails, file backups. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed. apps: casual web browsing. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed; first to drop otherwise. to ta l 1 0 0 m b ps qosc24 [7:6]_credit_c00 qosc28 [7:6]_credit_c10 goals total assured bandwidth (user defined) low drop probability (low-drop) high drop probability (high-drop) table 7 - two-dimensional world traffic zl50418 data sheet 34 zarlink semiconductor inc. qosc40 [7:6] and qosc48 [7:6] select these modes for the first and second gigabit ports, respectively. the default configuration for a 10/100 mbps port is th ree delay-bounded queues and one best-effort queue. the delay bounds per class are 0.8 ms for p3, 3.2 ms for p2, an d 12.8 ms for p1. for a 1 gbps port, we have a default of six delay-bounded queues and two best-effort queues. the delay bounds for a 1 gbps port are 0.16 ms for p7 and p6, 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. best effort traffic is only served when there is no delay-bounded traffic to be served. for a 1 gbps port where there are two best-effort queues p1 has strict priority over p0. we have a second configuration for a 10/100 mbps port in which there is one strict priority queue, two delay bounded queues and one best effort queue. the delay boun ds per class are 3.2 ms for p2 and 12.8 ms for p1. if the user is to choose this configuratio n, it is important that p3 (sp) traffic be either policed or implicitly bounded (e.g., if the incoming p3 traffic is very light and pr edictably patterned). strict priority traffic, if not admission-controlled at a prior stage to the zl50418 can ha ve a adverse effect on all other classes? performance. for a 1 gbps port, p7 and p6 are both sp classes, and p7 has strict priority over p6. in this case, the delay bounds per class are 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. the third configuration for a 10/100 mbps port contains one strict priority queue and three queues receiving a bandwidth partition via wfq. as in the second configuration, strict priority traffic needs to be carefully controlled. in the fourth configuration all queues are served using a wfq service discipline. 7.3 delay bound in the absence of a sophisticated qos server and si gnaling protocol, the zl50418 may not know the mix of incoming traffic ahead of time. to cope with this uncertai nty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (hol) qosc32 [7:6]_credit_c20 qosc36 [7:6]_credit_c30 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 8 - four qos configurations for a 10/100 mbps port p7 p6 p5 p4 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 9 - four qos configurations for a gigabit port zl50418 data sheet 35 zarlink semiconductor inc. frames. as a result we assure latency bounds for all admit ted frames with high confidence, even in the presence of system-wide congestion. our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. our algorithm also di fferentiates between high-drop and low-drop traffic with a weighted random early drop (wred) approach. random ear ly dropping prevents conges tion by randomly dropping a percentage of high-drop fram es even before the chip?s buffers are co mpletely full, while still largely sparing low-drop frames. this allows high-drop frames to be disc arded early, as a sacrifice for future low-drop frames. finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 strict priority and best effort when strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. two of our four qos configurations include st rict priority queues. the goal is for stri ct priority classes to be used for ietf expedited forwarding (ef), where performance guarantees are required. as we have indicated, it is important that strict priority traffic be either policed or implicitly b ounded, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. two of our four qos conf igurations include best effort queues. the goal is for best effort classes to be used for non-esse ntial traffic, because we provide no as surances about best effort performance. however, in a typical network settin g, much best effort traffic will indeed be transmitted and with an adequate degree of expediency. because we do not provide any delay assurances for best ef fort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is carefully controlled before entering the zl50418, we do not enforce a fair bandwidth partition by dr opping strict priority traffic. to summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. we only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 weighted fair queuing in some environments ? for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essent ial, wfq may be preferable to a delay-bounded scheduling discipline. the zl50418 provides the us er with a wfq option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. the user sets four wfq ?weights? (eight for gigabit ports) such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though we do not assure frame latency, the zl50418 still retains a set of dropping rules that helps to prevent congestion and trigger higher le vel protocol end-to-end flow control. as before, when strict priori ty is combined with wfq, we do not have sp ecial dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. however, we do indeed drop frames from sp queues for global buffer management purposes. in addition, queue p0 for a 10/100 port (and queues p0 and p1 for a gigabit port) are treat ed as best effort from a dropping perspective, though they still are assured a percent age of bandwidth from a wfq scheduling perspectiv e. what this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 shaper although traffic shaping is not a primary function of the zl50418, the chip does implement a shaper for expedited forwarding (ef). our goal in shaping is to control the peak and average rate of traffic exiting the zl50418. shaping is limited to the two gigabit ports only, and only to class p6 (the second highest priori ty). this means that class p6 will be the class used for ef traffic. if shaping is enabled for p6, then p6 traffic must be scheduled using strict priority. with reference to table 7, only t he middle two qos configurations may be used. peak rate is set using a programmable whole number, no grea ter than 64. for example, if the setting is 32, then the peak rate for shaped traffic is 32/64 * 1000 mbps = 500 mbps. average rate is also a programmable whole number, zl50418 data sheet 36 zarlink semiconductor inc. no greater than 64, and no greater than the peak rate. for example, if the setting is 16 , then the average rate for shaped traffic is 16/64 * 1000 mbps = 250 mbps. as a consequence of the above setti ngs in our example, shaped traffic will exit the zl50418 at a rate always less t han 500 mbps, and averaging no greater than 250 mbps. see programming qos register application note for more information. also, when shaping is enabled, it is possible for a p6 queue to explode in length if fed by a greedy source. the reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. though we do have global resource mana gement, we do nothing to prevent this situation locally. we assume sp traffic is policed at a prior stage to the zl50418. 7.7 rate control the zl50418 provides a rate control function on its 10/100 po rts. this rate control function applies to the outgoing traffic aggregate on each 10/100 port. it provides a way of reducing the outgoing average rate below full wire speed. note that the rate control function does not shap e or manipulate any particular traffic class. furthermore, though the average rate of the port can be controlled with this functi on, the peak rate will still be full line rate. two principal parameters are used to control the average rate for a 10/100 port. a port?s rate is controlled by allowing, on average, m bytes to be transmitted every n microseconds. both of these values are programmable. the user can program the number of bytes in 8-byte increments, and the time may be set in units of 10 ms. the value of m/n will, of co urse, equal the average data rate of the outgoing traffic aggregat e on the given 10/100 port. although there are many (m,n) pair s that will provide the same average da ta rate performanc e, the smaller the time interval n, the ?smoother? the output pa ttern will appear. in addition to controlling the avera ge data rate on a 10/100 port, the rate contro l function also manages the maximum burst size at wire speed. the maximum burst size can be considered the memory of the rate control mechanism; if the line has been idle for a long time, to what extent can the port ?make up for lost time? by transmitting a large burst? this value is also programmable, measured in 8-byte increments. example: suppose that the user wants to restrict fast ethernet port p?s average departure rate to 32 mbps ? 32% of line rate ? when the average is taken over a period of 10 ms. in an interval of 10 ms, exactly 40000 bytes can be transmitted at an average rate of 32 mbps. so how do we set the parameters? the rate control parame ters are contained in an internal ram block accessible through the cpu port (see programming qos registers a pplication note and processor interface application note). the data format is shown below. as we indicated earlier, the number of bytes is measured in 8-byte increments, so the 16-bit field ?number of bytes? should be set to (40000/8) 500. in addition, the time interval has to be indicated in units of 10 ms. though we want the average data rate on port p to be 32 mbps when measured over an interval of 10 ms, we can also adjust the maximum number of bytes that can be transmitted at full li ne rate in any single burst. su ppose we wish this limit to be 12 kilobytes. the number of bytes is measured in 8-by te increments, so the 16-bit field ?maximum burst size? is set to (12000/8) 1500. 63:40 39:32 31:16 15:0 0 time interval maximum burst size number of bytes zl50418 data sheet 37 zarlink semiconductor inc. 7.8 wred drop threshold management support to avoid congestion, the weighted random early detection (wred) logic drops packets according to specified parameters. the following table summarizes the behavior of the wred logic. figure 12 - behaviour of the wred logic px is the total byte count, in the priority queue x. the wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the prio rity queues. if delay bound scheduling is used, n equals p3*16+p2*4+p1. if using wfq scheduling, n equals p3+p 2+p1. each drop level from one to three has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. the x, y z percent c an be programmed by the register rdrc0, rdrc1. in level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. parameters a, b, c are the byte count thresholds for each priority queue. they can be programmed by the qo s control register (refer to the register group 5). see programming qos registers application note for more information. 7.9 buffer management because the number of fdb slots is a scarce resource and because we want to ensure that one misbehaving source port or class cannot harm the performance of a we ll-behaved source port or class, we introduce the concept of buffer management into the zl50418. our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in figure 13 on page 38. as shown in the figure, the fdb pool is divided into se veral parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a temp orary region is necessary, because when the frame first enters the zl50418, its destination port and class are as yet unknown and so the decision to drop or not needs to be temporarily postponed. this ensures that every frame ca n be received first before subjecting them to the frame drop discipline after classifying. six reserved sections, one for each of the first six prio rity classes, ensure a progra mmable number of fdb slots per class. the lowest two classes do no t receive any buffer reservation. furthermore, even for 10/100 mbps ports, a frame is stored in the region of the fdb corresponding to its class. as we have indicated, the eight classes use only four transmission scheduling queues for 10/100 mbps ports, but as far as buffer usage is concerned there are still eight distinguishable classes. another segment of the fdb reserves space for each of the 27 ports ? 26 ports for ethernet and one cpu port (port number 16). two parameters can be set, one for the source port reservation for 10/100 mbps ports and cpu port and one for the source port reservation for 1 gbps ports. these 27 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. in addition, there is a shared pool, wh ich can store any type of frame. the frame engine allocates the frames first in the six priority sections. when the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. once the shared poll is full the frames are allocated in the section reserved for the source port. in kb (kilobytes) p3 p2 p1 high drop low drop level 1 n 120 p3 akb p2 bkb p1 ckb x% 0% level 2 n 140 y% z% level 3 n 160 100% 100% zl50418 data sheet 38 zarlink semiconductor inc. the following registers define the size of each section of the frame data buffer: ? pr100- port reservation for 10/100 ports ? prg- port reservation for giga ports ? sfcb- share fcb size ? c2rs- class 2 reserve size ? c3rs- class 3 reserve size ? c4rs- class 4 reserve size ? c5rs- class 5 reserve size ? c6rs- class 6 reserve size ? c7rs- class 7 reserve size figure 13 - buffer partition scheme used to implement buffer management 7.9.1 dropping when buffers are scarce summarizing the two examples of local dr opping discussed earlier in this chapter: if a queue is a delay-bounded queue, we have a multile vel wred drop scheme designed to control delay and partition bandwidth in case of congestion. if a queue is a wfq-scheduled queue, we have a multile vel wred drop scheme designed to prevent congestion. in addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. the function of buffer management is to make sure that such dropping ca uses as little blocking as possible. 7.10 zl50418 flow control basics because frame loss is unacceptable for some applications , the zl50418 provides a flow control option. when flow control is enabled, scarcity of buffer space in the switch ma y trigger a flow control signal; this signal tells a source port that is sending a packet to this switch to temporarily hold off. shared pool s per-source reservations (24 10/100 m, cpu) temporary reservation per-class reservation zl50418 data sheet 39 zarlink semiconductor inc. while flow control offers the clear benefit of no packet loss , it also introduces a problem for quality of service. when a source port receives an ethernet fl ow control signal, all microflows origi nating at that port, well-behaved or not, are halted. a single packet destined for a congested ou tput can block other packet s destined for uncongested outputs. the resulting head-of-line bl ocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. in the zl50418, each source port can independently have flow control enabled or disabled. for flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. this is done so that those frames are not exposed to the wred dropping scheme. frames fr om flow control enabled ports feed to only one queue at the destination, the qu eue of lowest priority. what this means is that if flow control is enabled for a given source port, then we ca n guarantee that no packets originating from that port will be lo st, but at the possible expense of minimum bandwidth or maximum delay assur ances. in addition, these ?downgraded? frames may only use the shared pool or the per-source reserved pool in the fdb; frames from flow control enabled sources may not use reserved fdb slots for the highest six classes (p2-p7). the zl50418 does provide a syst em-wide option of permittin g normal qos scheduling (a nd buffer use) for frames originating from flow control enabled ports. when this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. the reason is that intelligent packet dropping is a major component of the zl50418?s approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.10.1 unicast flow control for unicast frames, flow control is trig gered by source po rt resource availability. re call that the zl50418?s buffer management scheme allocates a reserved number of fdb slots for each source port. if a programmed number of a source port?s reserved fdb slots have been used, then flow control xoff is triggered. xon is triggered when a port is currently being flow contro lled, and all of that port?s reserved fdb slots have been released. note that the zl50418?s per-source-port fdb reservations a ssure that a source port that sends a single frame to a congested destination will no t be flow controlled. 7.10.2 multicast flow control in unmanaged mode, flow control for mu lticast frames is triggered by a gl obal buffer counter. when the system exceeds a programmable threshold of multicast packets xoff is triggered. xon is trigge red when the system returns below this threshold. in managed mode, per-vlan flow control is used for mult icast frames. in this case, flow control is triggered by congestion at the destination. how so? the zl50418 ch ecks each destination to which a multicast packet is headed. for each destination port, the occupancy of the lowest-priority transmission multicast queue (measured in number of frames) is compared against a programmable congestion threshold. if cong estion is detected at even one of the packet?s destinations, then xoff is triggered. in addition, each source port has a 26-bit port map reco rding which port or ports of the multicast frame?s fanout were congested at the time xoff was triggered. all ports are continuously monitored for congestion, and a port is identified as uncongested when its que ue occupancy falls below a fixed thres hold. when all those ports that were originally marked as congested in the port map have become uncongested, then xon is triggered, and the 26-bit vector is reset to zero. the zl50418 also provides the option of disabling vlan multicast flow control. note: if per-port flow control is on, qos performance will be affected. zl50418 data sheet 40 zarlink semiconductor inc. 7.11 mapping to ietf diffserv classes the mapping between priority classes discussed in this chapter and elsewhere is shown below. as the table illustrates, p7 is used solely for netw ork management (nm) frames. p6 is used for expedited forwarding service (ef). classes p2 through p5 correspond to an assured forwarding (af) group of size 4. finally, p0 and p1 are two best effort (be) classes. for 10/100 mbps ports, the classes of table 9 are merged in pairs?one class corresponding to nm+ef, two af classes and a single be class. features of the zl50418 that correspond to the requir ements of their associated ietf classes are summarized in the table below. zl p7 p6 p5 p4 p3 p2 p1 p0 ietf nm ef af0 af1 af2 af3 be0 be1 table 10 - mapping between zl50418 and ietf diffserv classes for gigabit ports zl p3 p2 p1 p0 ietf nm+ef af0 af1 be0 table 11 - mapping between zl50418 and ietf diffserv classes for 10/100 ports network management (nm) and expedited forwarding (ef) global buffer reservation for nm and ef shaper for ef traffic on 1 gbps ports option of strict priority scheduling no dropping if admission controlled assured forwarding (af) four af classes for 1 gbps ports programmable bandwidth partition, with option of wfq service option of delay-bounded service keeps delay under fixed levels even if not admission-controlled random early discard, with programmable levels global buffer reservation for each af class best effort (be) two be classes for 1 gbps ports service only when other queues are idle means that qos not adversely affected random early discard, with programmable levels traffic from flow control enabled ports automatically classified as be table 12 - zl50418 features enabling ietf diffserv standards zl50418 data sheet 41 zarlink semiconductor inc. 8.0 port trunking 8.1 features and restrictions a port group (i.e., trunk) can include up to 4 physical ports, but when using stack all of the ports in a group must be in the same zl50418. the two gigabit ports may also be trunked together. there are three trunk groups total, including the option to trunk gigabit ports. load distribution among the ports in a trunk for unicast is performed using hashing based on source mac address and destination mac address. three other options incl ude source mac address only, destination mac address only and source port (in bidirectional ring mode only). load distribution for multicast is performed similarly. if a vlan includes any of the ports in a trunk group, all the ports in that trunk group should be in the same vlan member map. the zl50418 also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the zl50418 will automatically redistribute the traffic over to the remaining por ts in the trunk in unmanaged mode. in managed mode, the software can perform similar tasks. 8.2 unicast packet forwarding the search engine finds the destination mct entry and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. in addition, if the source address belongs to a trunk, then the source port?s trunk membership register is checked. a hash key, based on some combination of the source and destination mac addresses for the current packet, selects the appropriate forwarding port, as specified in the trunk_hash registers. 8.3 multicast packet forwarding for multicast packet forwarding, the de vice must determine the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multic ast packets to the appropriate destination ports in a port trunking environment. determining one forwarding port per group. preventing the multicast packet from looping back to the source trunk. the search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. this is because, when we select the prim ary forwarding port for each group, we do not take the source port into account. to prevent this, we simply apply one additional filter so as to block that forwarding port for this multicast packet. 8.4 unmanaged trunking in unmanaged mode, 3 trunk groups are supported. groups 0 and 1 can trunk up to 4 10/100 ports. group 2 can trunk 2 gigabit ports. the supported combinations are shown in the following table. group 0 port 0 port 1 port 2 port 3 !! table 13 - select via trunk0_mode register zl50418 data sheet 42 zarlink semiconductor inc. in unmanaged mode, the trunks are individua lly enabled/disabled by controlling pin trunk0,1,2. 9.0 port mirroring 9.1 port mirroring features the received or transmitted data of any 10/100 port in the zl50418 chip can be ?mirrored? to any other port. we support two such mirrored source-destination pairs. a mirror port can not also serve as a data port. 9.2 setting registers for port mirroring mirror1_src: sets the source port for the first port mirroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5 ] is used to select between ingress (rx) or egress (tx) data. mirror1_dest: sets the destination port fo r the first port mirroring pair. bits [4:0] select the de stination port to be mirrored. mirror2_src: sets the source port for the second port mi rroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5] is used to select between ingress (rx) or egress (tx) data. mirror2_dest: sets the destination port for the second port mirroring pair. bits [4:0] select the destination port to be mirrored. the default is port 0. refer to port mirroring applicat ion notes for further information. !!! !!!! group 1 port 4 port 5 port 6 port 7 ! ! ! !!! table 14 - select via trunk1_mode register group 2 port 25(giga 0) port 26 (giga 1) ! ! table 15 - unmanaged mode table 13 - select via trunk0_mode register zl50418 data sheet 43 zarlink semiconductor inc. 10.0 tbi interface 10.1 tbi connection the tbi interface can be used for 1000mbps fiber operati on. in this mode, the zl50418 is connected to the serdes as shown in figure 14. there are two tbi interfaces in the zl50418 devices. to enable to tbi function, the corresponding txen and txer pins need to be boot strapped. see ball ? signal description for details. figure 14 - tbi connection zl5041x serdes m25/26_txd[9:0] m25/26_txclk m25/26_rxclk m25/26_col m25/26_rxd[9:0] rbc0 rbc1 t[9:0] r[9:0] refclk zl50418 data sheet 44 zarlink semiconductor inc. 11.0 gpsi (7ws) interface 11.1 gpsi connection the 10/100 rmii ethernet port can function in gpsi (7ws) mode when the corresponding txen pin is strapped low with a 1 k pull down resistor. in this mode, the txd[0], tx d[1], rxd[0] and rxd[1] serve as tx data, tx clock, rx data and rx clock respectively. the link status and collision fr om the phy are multiplex ed and shifted into the switch device through external glue logic. the duplex of the port can be controlled by programming the ecr register. the gpsi interface can be operated in port based vlan mode only. figure 15 - gpsi (7ws) mode connection diagram 5041x port 0 ethernet phy crs rxd rx_clk tx_clk txd txen txd[1] txd[0] txen rxd[1] rxd[0] crs_dv port 15 ethernet phy link serializer (cpld) link0 link1 link2 link15 scan_link scan_clk collision serializer (cpld) col0 col1 col2 col15 scan_col zl50418 data sheet 45 zarlink semiconductor inc. 11.2 scan link and scan col interface an external cpld logic is required to take the link signals and collision sign als from the gpsi phys and shift them into the switch device. the switch devic e will drive out a signature to indicate the start of the sequence. after that, the cpld should shift in the link and collision status of the phys as shown in the figure. the extra link status indicates the polarity of the link signal. one indicate s the polarity of the link signal is active high. figure 16 - scan link and sc an collison status diagram 12.0 led interface 12.1 led interface introduction a serial output channel provides port status information fr om the zl50418 chips. it requires three additional pins. led_clk at 12.5 mhz led_syn a sync pulse that defines the boundary between status frames led_data a continuous serial stream of data for all status leds that repeats once every frame time a non-serial interf ace is also allowed, but in this case only the gigabit ports will have status leds. a low cost external device (44 pin pal) is used to decode the serial data and to drive an led array for display. this device can be customized for different needs. 12.2 port status in the zl50418, each port has 8 status indicators each repr esented by a single bit. the 8 led status indicators are: ? bit 0: flow control ? bit 1:transmit data ? bit 2: receive databit 3: activity (where activi ty includes either transmission or reception of data) ? bit 4: link up ? bit 5: speed (1= 100 mb/s; 0= 10 mb/s) ? bit 6: full-duplex ? bit 7: collision eight clocks are required to cycle through the eight status bits for each port. scan_clk scan_link/ scan_col drived by zl5041x drived by cpld 25 cycles for link/ 24 cycles for col total 32 cycles period zl50418 data sheet 46 zarlink semiconductor inc. when the led_syn pulse is asserted, the led interface will present 256 le d clock cycles with the clock cycles providing information fo r the following ports. ? port 0 (10/100): cycles #0 to cycle #7 ? port 1 (10/100): cycles#8 to cycle #15 ? port 2 (10/100): cycle #16 to cycle #23 ?... ? port 14(10/100): cycle #112 to cycle #119 ? port 15(10/100): cycle #120 to cycle #127 ? port 24 (gigabit 1): cycle #192 to cycle #199 ? port 25 (gigabit 2): cycle #200 to cycle #207 ? byte 26 (additional status): cycle #208 to cycle #215 ? byte 27 (additional status): cycle #216 to cycle #223 cycles #224 to 256 present data with a value of zero. the first two bits of byte 26 provides the speed information for the gigabit ports while the remainder of byte 26 and byte 27 provides bist status ? 26[0]: g0 port (1= port 24 is operating at gigabit speed; 0= speed is either 10 or 100 mb/s depending on speed bit of port 24) ? 26[1]: g1 port (1= port 25 is operating at gigabit speed; 0= speed is either 10 or 100 mb/s depending on speed bit of port 25) ? 26[2]: initialization done ? 26[3]: initialization start ? 26[4]: checksum ok ? 26[5]: link_init_complete ? 26[6]: bist_fail ? 26[7]: ram_error ? 27[0]: bist_in_process ? 27[1]: bist_done 12.3 led interface timing diagram the signal from the zl50418 to the led decoder is shown in figure 17. . figure 17 - timing diagram of led interface zl50418 data sheet 47 zarlink semiconductor inc. 13.0 hardware statistics counter 13.1 hardware statistics counters list zl50418 hardware provides a full set of statistics c ounters for each ethernet port. the cpu accesses these counters through the cp u interface. all hardware counters are rollo ver counters. when a counter rolls over, the cpu is interrupted, so that long-term statistics may be ke pt. the mac detects all statistics, except for the delay exceed discard counter (detected by buffer manager) a nd the filtering counter (detected by queue manager). the following is the wrapped signal sent to the cpu through the command block. 31 30 26 25 0 status wrapped signal b[0] 0-d bytes sent (d) b[1] 1-l unicast frame sent b[2] 1-u frame send fail b[3] 2-i flow control frames sent b[4] 2-u non-unicast frames sent b[5] 3-d bytes received (good and bad) (d) b[6] 4-d frames received (good and bad) (d) b[7] 5-d total bytes received (d) b[8] 6-l total frames received b9] 6-u flow control frames received b[10] 7-l multicast frames received b[11] 7-u broadcast frames received b[12] 8-l frames with length of 64 bytes b[13] 8-u jabber frames b[14] 9-l frames with length between 65-127 bytes b[15] 9-u oversize frames b[16] a-l frames with length between 128-255 bytes b[17] a-u frames with length between 256-511 bytes b[18] b-l frames with length between 512-1023 bytes b[19] b-u frames with length between 1024-1528 bytes b[20] c-l fragments b[21] c-u1 alignment error b[22] c-u undersize frames b[23] d-l crc b[24] d-u short event b[25] e-l collision b[26] e-u drop b[27] f-l filtering counter b[28] f-u1 delay exceed discard counter zl50418 data sheet 48 zarlink semiconductor inc. 13.2 eee 802.3 hub management (rfc 1516) 13.2.1 event counters 13.2.1.1 r eadable o ctet counts number of bytes (i.e. octets) contained in good valid frames received. 13.2.1.2 readableframe counts number of good valid frames received. b[29] f-u late collision b[30] link status change b[31] current link status notation: x-y x: address in the contain memory y: size and bits for the counter d: d word counter l: 24 bits counter bit [23:0] u: 8 bits counter bit [31:24] u1: 8 bits counter bit [23:16] l: 16 bits counter bit [15:0] u: 16 bits counter bit [31:16] frame size: > 64 bytes, < 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no fcs (i.e. checksum) error no collisions frame size: > 64 bytes, < 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no fcs error no collisions zl50418 data sheet 49 zarlink semiconductor inc. 13.2.1.3 fcserrors counts number of valid frames received with bad fcs. 13.2.1.4 alignmenterrors counts number of valid frames received with bad alignment (not byte-aligned). 13.2.1.5 frametoolongs counts number of frames received with size exceeding the maximum allowable frame size. 13.2.1.6 shortevents counts number of frames received with size less than the length of a short event. frame size: > 64 bytes, < 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no framing error no collisions frame size: > 64 bytes, < 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged no framing error no collisions frame size: > 64 bytes, > 1522 bytes if vlan tagged; 1518 bytes if not vlan tagged fcs error: don?t care framing error: don?t care no collisions frame size: < 10 bytes fcs error: don?t care framing error: don?t care no collisions zl50418 data sheet 50 zarlink semiconductor inc. 13.2.1.7 runts counts number of frames received with size under 64 bytes, but greater than the length of a short event. 13.2.1.8 collisions counts number of collision events. 13.2.1.9 lateevents counts number of collision events that occurred late (after lateeventth reshold = 64 bytes). 13.2.1.10 verylongevents counts number of frames received with size larg er than jabber lockup protection timer (tw3). 13.2.1.11 dataratemisatches for repeaters or hub application only. 13.2.1.12 autopartitions for repeaters or hub application only. 13.2.1.13 totalerrors sum of the following errors: fcs errors alignment errors frame too long short events late events very long events frame size: > 10 bytes, < 64 bytes fcs error: don?t care framing error: don?t care no collisions frame size: any size frame size: any size events are also count ed by collision counter frame size: > jabber zl50418 data sheet 51 zarlink semiconductor inc. 13.3 ieee ? 802.1 brid ge management (rfc 1286) 13.3.1 event counters 13.3.1.1 inframes counts number of frames received by this port or segment. note: a frame received by this port is only counted by this co unter if and only if it is for a protocol being processed by the local bridge function. 13.3.1.2 outframes counts number of frames transmitted by this port. note : a frame transmitted by this port is only counted by th is counter if and only if it is for a protocol being processed by the local bridge function. 13.3.1.3 indiscards counts number of valid frames received which were di scarded (i.e., filtered) by the forwarding process. 13.3.1.4 delayexceededdiscards counts number of frames discarded due to excessive transmit delay through the bridge. 13.3.1.5 mtuexceededdiscards counts number of frames discarded due to excessive size. 13.4 rmon ? ethernet statistic group (rfc 1757) 13.4.1 event counters 13.4.1.1 drop events counts number of times a packet is dropped, because of lack of available resources. does not include all packet dropping -- for example, random early drop for quality of service support. 13.4.1.2 octets counts the total number of octets (i.e. bytes) in any frames received. 13.4.1.3 broadcastpkts counts the number of good frames received and forwarded with broadcast address. does not include non-broadcast multicast frames. 13.4.1.4 multicastpkts counts the number of good frames received and forwarded with multicast address. does not include broadcast frames. zl50418 data sheet 52 zarlink semiconductor inc. 13.4.1.5 crcalignerrors counts number of frames received with fcs or alignment errors 13.4.1.6 undersizepkts counts number of frames received with size less than 64 bytes. 13.4.1.7 oversizepkts counts number of frames received with size exceeding the maximum allowable frame size. 13.4.1.8 fragments counts number of frames received with size less than 64 bytes and with bad fcs. 13.4.1.9 jabbers counts number of frames received with size exceeding maximum frame size and with bad fcs. frame size: > 64 bytes, < 1522 bytes if vlan tag (1518 if no vlan) no collisions: frame size: < 64 bytes, no fcs error no framing error no collisions frame size: 1522 bytes if vlan tag (1518 bytes if no vlan) fcs error don?t care framing error don?t care no collisions frame size: < 64 bytes framing error don?t care no collisions frame size: > 1522 bytes if vlan tag (1518 bytes if no vlan) framing error don?t care no collisions zl50418 data sheet 53 zarlink semiconductor inc. 13.4.1.10 collisions counts number of collis ion events detected. only a best estimate since collisions can only be detected while in transmit mode, but not while in receive mode. 13.4.1.11 packet count for different size groups six different size groups ? one counter for each: ? pkts64octets for any packet with size = 64 bytes ? pkts65to127octets for any packet with size from 65 bytes to 127 bytes ? pkts128to255octets for any packet with size from 128 bytes to 255 bytes ? pkts256to511octets for any packet with size from 256 bytes to 511 bytes ? pkts512to1023octets for any packet with size from 512 bytes to 1023 bytes ? pkts1024to1518octets for any packet with size from 1024 bytes to 1518 bytes counts both good and bad packets. 13.5 miscellaneous counters in addition to the statistics groups defined in previous se ctions, the zl50418 has other statistics counters for its own purposes. we have two counters for flow control ? one counting the number of flow control frames received and another counting the number of flow control frames sent. we also have two counters, one for unicast frames sent and one for non-unicast frames sent. a broadcast or mu lticast frame qualifies as non-unicast. furthermore, we have a counter called ?frame se nd fail.? this keeps track of fifo under-runs, late collis ions, and collisions that have occurred 16 times. frame size: any size zl50418 data sheet 54 zarlink semiconductor inc. 14.0 regist er definition 14.1 zl50418 register description register description cpu addr (hex) r/w i 2 c addr (hex) default notes 0. ethernet port control registers subs titute [n] with port number (0..f,18..1a) ecr1p?n? port control register 1 for port n 0000 + 2 x n r/w 000-01 a 020 ecr2p?n? port control register 2 for port n 001 + 2 x n r/w 01b-03 5 000 ggc extra giga bit control register 036 r/w na 000 1. vlan control registers substitute [n] with port number (0..f,18..1a) avtcl vlan type code register low 100 r/w 036 000 avtch vlan type code register high 101 r/w 037 081 pvmap?n?_0 port ?n? configuration register 0 102 + 4n r/w 038-052 0ff pvmap?n?_1 port ?n? configuration register 1 103 + 4n r/w 053-06 d 0ff pvmap?n?_3 port ?n? configuration register 3 105 + 4n r/w 089-0a 3 007 pvmode vlan operating mode 170 r/w 0a4 000 pvroute7-0 vlan router group enable 171-178 r/w na 000 2. trunk control registers trunk0_l trunk group 0 low 200 r/w na 000 trunk0_m trunk group 0 medium 201 r/w na 000 trunk0_ mode trunk group 0 mode 203 r/w 0a5 003 trunk0_ hash0 trunk group 0 hash 0 destination port 204 r/w na 000 trunk0_ hash1 trunk group 0 hash 1 destination port 205 r/w na 001 trunk0_ hash2 trunk group 0 hash 2 destination port 206 r/w na 002 trunk0_ hash3 trunk group 0 hash 3 destination port 207 r/w na 003 trunk1_l trunk group 1 low 208 r/w na 000 trunk1_m trunk group 1 medium 209 r/w na 000 trunk1_ mode trunk group 1 mode 20b r/w 0a6 003 zl50418 data sheet 55 zarlink semiconductor inc. trunk1_ hash0 trunk group 1 hash 0 destination port 20c r/w na 004 trunk1_ hash1 trunk group 1 hash 1 destination port 20d r/w na 005 trunk1_ hash2 trunk group 1 hash 2 destination port 20e r/w na 006 trunk1_ hash3 trunk group 1 hash 3 destination port 20f r/w na 007 trunk2_ mode trunk group 2 mode 210 r/w na 003 trunk2_ hash0 trunk group 2 hash 0 destination port 211 r/w na 019 trunk2_ hash1 trunk group 2 hash 1 destination port 212 r/w na 01a multicast_ hash0-0 multicast hash resu lt 0 mask byte 0 220 r/w na 0ff multicast_ hash0-1 multicast hash resu lt 0 mask byte 1 221 r/w na 0ff multicast_ hash0-2 multicast hash resu lt 0 mask byte 2 222 r/w na 0ff multicast_ hash0-3 multicast hash resu lt 0 mask byte 3 223 r/w na 0ff multicast_ hash1-0 multicast hash resu lt 1 mask byte 0 224 r/w na 0ff multicast_ hash1-1 multicast hash resu lt 1 mask byte 1 225 r/w na 0ff multicast_ hash1-2 multicast hash resu lt 1 mask byte 2 226 r/w na 0ff multicast_ hash1-3 multicast hash resu lt 1 mask byte 3 227 r/w na 0ff multicast_ hash2-0 multicast hash resu lt 2 mask byte 0 228 r/w na 0ff multicast_ hash2-1 multicast hash resu lt 2 mask byte 1 229 r/w na 0ff multicast_ hash2-2 multicast hash resu lt 2 mask byte 2 22a r/w na 0ff multicast_ hash2-3 multicast hash resu lt 2 mask byte 3 22b r/w na 0ff register description cpu addr (hex) r/w i 2 c addr (hex) default notes zl50418 data sheet 56 zarlink semiconductor inc. multicast_ hash3-0 multicast hash resu lt 3 mask byte 0 22c r/w na 0ff multicast_ hash3-1 multicast hash resu lt 3 mask byte 1 22d r/w na 0ff multicast_ hash3-2 multicast hash resu lt 3 mask byte 2 22e r/w na 0ff multicast_ hash3-3 multicast hash resu lt 3 mask byte 3 22f r/w na 0ff 3. cpu port configuration mac0 cpu mac address byte 0 300 r/w na 000 mac1 cpu mac address byte 1 301 r/w na 000 mac2 cpu mac address byte 2 302 r/w na 000 mac3 cpu mac address byte 3 303 r/w na 000 mac4 cpu mac address byte 4 304 r/w na 000 mac5 cpu mac address byte 5 305 r/w na 000 int_mask0 interrupt mask 0 306 r/w na 000 intp_mask?n? interrupt mask for mac port 2n, 2n+1 310+n (310 -313) r/w na 000 rqs receive queue select 323 r/w na 000 rqss receive queue status 324 ro na n/a tx_age transmission queue aging time 325 r/w 0a7 008 4. search engine configurations agetime_low mac address agin g time low 400 r/w 0a8 2m:05c/ 4m:02e agetime_ high mac address aging time high 401 r/w 0a9 000 v_agetime vlan to port aging time 402 r/w na 0ff se_opmode search engine operating mode 403 r/w na 000 scan scan control register 404 r/w na 000 5. buffer control and qos control fcbat fcb aging timer 500 r/w 0aa 0ff qosc qos control 501 r/w 0ab 000 fcr flooding control register 502 r/w 0ac 008 register description cpu addr (hex) r/w i 2 c addr (hex) default notes zl50418 data sheet 57 zarlink semiconductor inc. avpml vlan priority map low 503 r/w 0ad 000 avpmm vlan priority map middle 504 r/w 0ae 000 avpmh vlan priority map high 505 r/w 0af 000 tospml tos priority map low 506 r/w 0b0 000 tospmm tos priority map middle 507 r/w 0b1 000 tospmh tos priority map high 508 r/w 0b2 000 avdm vlan discard map 509 r/w 0b3 000 tosdml tos discard map 50a r/w 0b4 000 bmrc broadcast/multicast ra te control 50b r/w 0b5 000 ucc unicast congestion control 50c r/w 0b6 2m:008/ 4m:010 mcc multicast congestion control 50d r/w 0b7 050 pr100 port reservation for 10/100 ports 50e r/w 0b8 2m:024/ 4m:036 prg port reservation for giga ports 50f r/w 0b9 2m:035/ 4m:058 sfcb share fcb size 510 r/w 0ba 2m:014/ 4m:064 c2rs class 2 reserve size 511 r/w 0bb 000 c3rs class 3 reserve size 512 r/w 0bc 000 c4rs class 4 reserve size 513 r/w 0bd 000 c5rs class 5 reserve size 514 r/w 0be 000 c6rs class 6 reserve size 515 r/w 0bf 000 c7rs class 7 reserve size 516 r/w 0c0 000 qosc?n? qos control (n=0 - 5) 517- 51c r/w 0c1-0c 6 000 qos control (n=6 - 11) 51d- 522 r/w na 000 qos control (n=12 - 23) 523- 52e r/w 0c7-0d 2 000 qos control (n=24 - 59) 52f- 552 r/w na 000 rdrc0 wred drop rate control 0 553 r/w 0fb 08f rdrc1 wred drop rate control 1 554 r/w 0fc 088 register description cpu addr (hex) r/w i 2 c addr (hex) default notes zl50418 data sheet 58 zarlink semiconductor inc. user_ port?n?_low user define logical port ?n? low (n=0-7) 580 + 2n r/w 0d6-0d d 000 user_ port?n?_high user define logical port ?n? high 581 + 2n r/w 0de-0e 5 000 user_ port1:0_ priority user define logic port 1 and 0 priority 590 r/w 0e6 000 user_ port3:2_ priority user define logic port 3 and 2 priority 591 r/w 0e7 000 user_ port5:4_ priority user define logic port 5 and 4 priority 592 r/w 0e8 000 user_ port7:6_pri ority user define logic port 7 and 6 priority 593 r/w 0e9 000 user_port_ enable user define logic port enable 594 r/w 0ea 000 wlpp10 well known logic port priority for 1 and 0 595 r/w 0eb 000 wlpp32 well known logic port priority for 3 and 2 596 r/w 0ec 000 wlpp54 well known logic port priority for 5 and 4 597 r/w 0ed 000 wlpp76 well-known logic port priority for 7 & 6 598 r/w 0ee 000 wlpe well known logic port enable 599 r/w 0ef 000 rlowl user define range low bit 7:0 59a r/w 0f4 000 rlowh user define range low bit 15:8 59b r/w 0f5 000 rhighl user define range high bit 7:0 59c r/w 0d3 000 rhighh user define range high bit 15:8 59d r/w 0d4 000 rpriority user define range priority 59e r/w 0d5 000 cpuqosc1~3 byte limit for txq on cpu port 5a0-5a2 r/w na 000 6. misc configuration registers mii_op0 mii register option 0 600 r/w 0f0 000 mii_op1 mii register option 1 601 r/w 0f1 000 fen feature registers 602 r/w 0f2 010 register description cpu addr (hex) r/w i 2 c addr (hex) default notes zl50418 data sheet 59 zarlink semiconductor inc. miic0 mii command register 0 603 r/w n/a 000 miic1 mii command register 1 604 r/w n/a 000 miic2 mii command register 2 605 r/w n/a 000 miic3 mii command register 3 606 r/w n/a 000 miid0 mii data register 0 607 ro n/a n/a miid1 mii data register 1 608 ro n/a n/a led led control register 609 r/w 0f3 000 sum eeprom checksum register 60b r/w 0ff 000 7. port mirroring controls mirror1_src port mirror 1 source port 700 r/w n/a 07f mirror1_ dest port mirror 1 destination port 701 r/w n/a 017 mirror2_src port mirror 2 source port 702 r/w n/a 0ff mirror2_ dest port mirror 2 destination port 703 r/w n/a 000 f. device configuration register gcr global control register f00 r/w n/a 000 dcr device status and signature register f01 ro n/a n/a dcr1 giga port status f02 ro n/a n/a dpst device port status register f03 r/w n/a 000 dtst data read back register f04 ro n/a n/a da da register fff ro n/a da register description cpu addr (hex) r/w i 2 c addr (hex) default notes zl50418 data sheet 60 zarlink semiconductor inc. 14.2 directly accessed registers 14.2.1 index_reg0 ? address bits [7:0] for indirectly accessed register addresses ? address = 0 (write only) 14.2.2 index_reg1 (only needed for 8-bit mode) ? address bits [15:8] for indirectly accessed register addresses ? address = 1 (write only) 14.2.3 data_frame_reg ? data of indirectly accessed registers. (8 bits) ? address = 2 (read/write) 14.2.4 control_frame_reg ? cpu transmit/receive switch frames. (8/16 bits) ? address = 3 (read/write) ?format: - send frame from cpu: in sequence) - frame data (size should be in multiple of 8-byte) - 8-byte of frame status (frame size, destination port #, frame o.k. status) - cpu received frame: in sequence) - 8-byte of frame status (frame size, source port #, vlan tag) - frame data 14.2.5 command&status register ? cpu interface commands (write) and status ? address = 4 (read/write) ? when the cpu writes to this register bit [0]: ? set control frame receive buffer ready, after cpu writes a complete frame into the buffer. this bit is self-cleared. bit [1]: ? set control frame transmit buffer1 ready, after cpu reads out a complete frame from the buffer. this bit is self-cleared. bit [2]: ? set control frame transmit buffer2 ready, after cpu reads out a complete frame from the buffer. this bit is self-cleared. bit [3]: ? set this bit to indicate cpu received a whole frame (transmit fifo frame receive done), and flushed the rest of fram e fragment, if occurs. this bit will be self-cleared. bit [4]: ? set this bit to indicate that the following write to the receive fifo is the last one (eof). this bit will be self-cleared. zl50418 data sheet 61 zarlink semiconductor inc. when the cpu reads this register: 14.2.6 interrupt register ? interrupt sources (8 bits) ? address = 5 (read only) when cpu reads this register bit [5]: ? set this bit to re-start the data that is sent from the cpu to receive fifo (re-align). this feature can be used for software debug. for normal operation must be '0'. bit [6]: ? do not use. must be '0' bit [7]: ? reserved bit [0]: ? control frame receive buffer ready, cpu can write a new frame - 1 ? cpu can write a new control command 1 - 0 ? cpu has to wait until this bit is 1 to write a new control command 1 bit [1]: ? control frame transmit buffer1 ready for cpu to read - 1 ? cpu can read a new control command 1 - 0 ? cpu has to wait until this bit is 1 to read a ne w control command bit [2]: ? control frame transmit buffer2 ready for cpu to read - 1 ? cpu can read a new control command 1 - 0 ? cpu has to wait until this bi t is 1 to read a new control command bit [3]: ? transmit fifo has data for cpu to read (txfifo_rdy) bit [4]: ? receive fifo has space for incoming cpu frame (rxfifo_spok) bit [5]: ? transmit fifo end of frame (txfifo_eof) bit [6]: ? reserve bit [7]: ? reserve bit [0]: ? cpu frame interrupt bit [1]: ? control frame 1 interrupt. control frame receive buffer1 has data for cpu to read bit [2]: ? control frame 2 interrupt. control frame receive buffer2 has data for cpu to read bit [3]: ? gigabit port a interrupt bit [4]: ? gigabit port b interrupt bit [7:3]: ? reserve note: this register is not self-c leared. after reading cpu has to clear the bit writing 0 to it. zl50418 data sheet 62 zarlink semiconductor inc. 14.2.7 control command frame buffer1 access register ? address = 6 (read/write) ? when cpu writes to this register, data is wri tten to the control command frame receive buffer ? when cpu reads this register, data is read from the control command frame transmit buffer1 14.2.8 control command frame buffer2 access register ? address = 7 (read only) ? when cpu reads this register, data is read from the control command frame transmit buffer1 indirectly accessed registers 14.3 (group 0 address) mac ports group 14.3.1 ecr1pn: po rt n control register i 2 c address 000 - 01a; cpu address:0000+2xn (n = port number) accessed by cpu, serial interface and i 2 c (r/w) 76543210 sp state a-fc port mode bit [0] ? 1 - flow control off ? 0 - flow control on ? when flow control on: ? in half duplex mode the mac transmitter applies back pressure for flow control. ? in full duplex mode the mac transmitter sends flow control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the flow control frame received counter is incremented whenever a flow control is received. ? when flow control off: ? in half duplex mode the mac transmitter does not assert flow control by sending flow control frames or jamming collision. ? in full duplex mode the mac transmitter does not send flow control frames. the mac receiver does not interpret or proc ess the flow control frames. the flow control frame received counter is not incremented. bit [1] - 1 - half duplex - only in 10/100 mode - 0 - full duplex bit [2] - 1 - 10mbps - 0 - 100mbps zl50418 data sheet 63 zarlink semiconductor inc. 14.3.2 ecr2pn: po rt n control register i 2 c address: 01b-035; cpu address:0001+2xn (n = port number) accessed by cpu and serial interface (r/w) bit [4:3] - 00 ? automatic enable auto neg. - this enables hardware state machine for auto-negotiation. - 01 - limited disable auto neg. this disables hardware for speed auto-negotiation. hardware poll mii for link status. - 10 - link down. force link down (disable the port). - 11 - link up. the configuration in ecr1[2:0] is used for (speed/half duplex/full duplex/flow control) setup. bit [5] ? asymmetric flow control enable. - 0 ? disable asymmetric flow control - 01 ? enable asymmetric flow control - when this bit is set, and flow control is on (bit [0] = 0), don?t send out a flow control frame. but mac receiver interprets and processes flow control frames. bit [7:6] ? ss - spanning tree state (802.1d spanning tree protocol) default is 11 . - 00 ? blocking: frame is dropped - 01 - listening: frame is dropped - 10 - learning: frame is dropped. source mac address is learned. - 11 - forwarding: frame is forwarded. source mac address is learned. 7 6 543 2 10 security en qos sel reserve disl ftf futf bit [0]: ? filter untagged frame ( default 0 ) -0: disable - 1: all untagged frames from this port ar e discarded or follow security option when security is enable bit [1]: ? filter tag frame ( default 0 ) -0: disable - 1: all tagged frames from this port are discarded or follow security option when security is enable bit [2]: ? learning disable (default 0) - 1 learning is disabled on this port - 0 learning is enabled on this port bit [3]: ? must be ?1? bit [5:4:] ? qos mode selection (default 00) ? determines which of the 4 sets of qos settings is used for 10/100 ports. ? note that there are 4 sets of per-queue byte thresholds, and 4 sets of wfq ratios programmed. these bits select among the 4 choices for each 10/100 port. refer to qos application note. ? 00: select class byte limit set 0 and classes wfq credit set 0 ? 01: select class byte limit set 1 and classes wfq credit set 1 ? 10: select class byte limit set 2 and classes wfq credit set 2 ? 11: select class byte limit set 3 and classes wfq credit set 3 zl50418 data sheet 64 zarlink semiconductor inc. 14.3.3 ggcontrol ? extra giga port control ? cpu address:h036 ? accessed by cpu and serial interface (r/w) bit [7:6] ? security enable (default 00). the zl50418 checks the incoming data for one of the following conditions: 1. if the source mac address of the incoming packet is in the mac table and is defined as secure address but the ingress port is not the same as the port associated with the mac address in the mac table. a mac address is defined as secure when its entry at mac table has static status and bit 0 is set to 1. mac addre ss bit 0 (the first bit transmitted) indi- cates whether the address is unicast or multicast. as source addresses are always unicast bit 0 is not used (always 0). zl50418 uses this bit to define secure mac addresses. 2. if the port is set as learning disable and the source mac address of the incoming packet is not defined in the mac address table. 3. if the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. if one of these thre e conditions occurs, the pa cket will be handled accord- ing to one of the following specified options: ? cpu installed ? 00 ? disable port security ? 01 ? discard violating packets ? 10 ? send packet to cpu and destination port ? 11 ? send packet to cpu only 7654 32 1 0 df miib rsta df miia rsta bit [0]: ? reset giga port a - 0: normal operation (default) - 1: reset gigabit port a. normally used when a new phy is connected (hot swap). bit [1]: ? giga port a use mii interface (10/100 m) - 0: gigabit port operations at 1000 mode (default) - 1: gigabit port operations at 10/100 mode bit [2]: ? reserved - must be zero bit [3]: ? giga port a direct flow control (mac to mac connection). the zl50418 supports direct flow control mechanism; the flow control frame is therefore not sent through the gigabit port data path. - 0: direct flow control disabled (default) - 1: direct flow control enabled bit [4]: ? reset giga port b - 0: normal operation (default) - 1: reset giga bit port b zl50418 data sheet 65 zarlink semiconductor inc. 14.4 (group 1 address) vlan group 14.4.1 avtcl ? vlan type code register low i 2 c address 036; cpu address:h100 accessed by cpu, serial interface and i 2 c (r/w) 14.4.2 avtch ? vlan type code register high i 2 c address 037; cpu address:h101 accessed by cpu, serial interface and i 2 c (r/w) 14.4.3 pvmap00_0 ? port 00 configuration register 0 i 2 c address 038, cpu address:h102 accessed by cpu, serial interface and i 2 c (r/w) in port based vlan mode this register indicates the legal egress ports. a ?1? on bit 7 means that the packet can be sent to port 7. a ?0? on bit 7 means that any packet desti ned to port 7 will be discarded. this register works with registers 1, 2 and 3 to form a 27 bit mask to all egress ports. in tag based vlan mode this is the default vlan tag. it works with configur ation register pvmap00_1 [7:5] [3:0] to form a default vlan tag. if the received packet is untagged, then the pa cket is classified with the default vlan tag. if the received packet has a vlan id of 0, then pvid is used to replace the packet?s vlan id. bit [5]: ? giga port b use mii interface (10/100 m) - 0: gigabit port operates at 1000 mode (default) - 1: gigabit port operates at 10/100 mode bit [6]: ? reserved - must be zero bit [7]: ? giga port b direct flow control (mac to mac connection). zl50418 supports direct flow control mechanism; the flow control frame is therefore not sent through the gigabit port data path. - 0: direct flow control disabled (default) - 1: direct flow control enabled bit [7:0]: vlantype_low: lower 8 bits of the vlan type code (default 00) bit [7:0]: vlantype_high: upper 8 bits of the vlan type code (default is 81) bit [7:0]: vlan mask for ports 7 to 0 (default ff) bit [7:0]: pvid [7:0] (default is ff) zl50418 data sheet 66 zarlink semiconductor inc. 14.4.4 pvmap00_1 ? port 00 configuration register 1 i 2 c address h53, cpu address:h103 accessed by cpu, serial interface and i 2 c (r/w) in port based vlan mode in tag based vlan mode 14.4.5 pvmap00_3 ? port 00 configuration register 3 i 2 c address h89, cpu address:h105) accessed by cpu, serial interface and i 2 c (r/w) in port based vlan mode bit [7:0]: vlan mask for ports 15 to 8 (default is ff) 7543 0 unitag port prio rity ultrust pvid bit [3:0]: pvid [11:8] (default is f) bit [4]: ? untrusted port. (default is 1) this register is used to change the vlan priority field of a packet to a predetermined priority. - 1 : vlan priority field is ch anged to bit[7:5] at ingress port - 0 : keep vlan priority field bit [7:5]: ? untag port priority (default 7) 765 32 0 fp en drop default tx priority vlan mask bit [2:0]: vlan mask for ports 26 to 24 (default 7). port 24 is the cpu port bit [5:3]: default transmit pr iority. used when bit[7]=1 (default 0) - 000 transmit priority level 0 (lowest) - 001 transmit priority level 1 - 010 transmit priority level 2 - 011 transmit priority level 3 - 100 transmit priority level 4 - 101 transmit priority level 5 - 110 transmit priority level 6 - 111 transmit priority level 7 (highest) zl50418 data sheet 67 zarlink semiconductor inc. in tag-based vlan mode bit [6]: default discard priority. used when bit[7]=1 (default 0) - 0 - discard priority level 0 (lowest) - 1 - discard priority level 1(highest) bit [7]: enable fix priority ( default 0 ) - 0 disable fix priority. all fr ames are analyzed. transmit priority and discard priority are based on vlan tag, tos or logical port. - 1 transmit priority and discard priority are based on values programmed in bit [6:3] bit [0]: ? not used bit [1]: ingress filter enable (default 1) - 0 disable ingress filter. packets with vlan not belonging to source port are forwarded, if destination port belongs to the vlan. symmetric vlan. - 1 enable ingress filter . packets with vlan no t belonging to source port are filtered. asymmetric vlan. bit [2]: force untag out (vlan tagging is based on 802.1q rule) (default 1). - 0 disable (default) - 1 force untagged output all packets transmitted from this po rt are untagged. this register is used when this port is connected to legacy equipment that does not support vlan tagging. bit [5:3]: default transmit priority. used when bit [7]=1 (default 0) - 000 transmit priority level 0 (lowest) - 001 transmit priority level 1 - 010 transmit priority level 2 - 011 transmit priority level 3 - 100 transmit priority level 4 - 101 transmit priority level 5 - 110 transmit priority level 6 - 111 transmit priority level 7 (highest) bit [6]: default discard prio rity used when bit [7]=1 (default 0) - 0 discard priority level 0 (lowest) - 1 discard priority level 1 (highest) bit [7]: enable fix priority (default 0) - 0 disable fix priority. all frames are analyzed. transmit priority and discard priority are based on vlan tag, tos or logical port. - 1 transmit priority and discard priority are based on values programmed in bit [6:3] zl50418 data sheet 68 zarlink semiconductor inc. 14.5 port configuration registers pvmap01_0,1,3 i 2 c address h39,54,8a; cpu address:h106, 107, 109 pvmap02_0,1,3 i 2 c address h3a, 55,8b; cp u address:h10a, 10b, 10d pvmap03_0,1,3 i 2 c address h3b,56,8c; cpu address:h10e, 10f, 111 pvmap04_0,1,3 i 2 c address h3c,57,8d; cpu address:h112, 113, 115 pvmap05_0,1,3 i 2 c address h3d,58,8e; cpu address:h116, 117, 119 pvmap06_0,1,3 i 2 c address h3e,59,8f; cpu address:h11a, 11b, 11d pvmap07_0,1,3 i 2 c address h3f,5a,90; cpu address:h11e, 11f, 121 pvmap08_0,1,3 i 2 c address h40,5b,91; cpu address:h122, 123, 125 pvmap09_0,1,3 i 2 c address h41,5c,92; cpu address:h126, 127, 129 pvmap10_0,1,3 i 2 c address h42,5d,93; cpu address:h12a, 12b, 12d pvmap11_0,1,3 i 2 c address h43,5e,94; cpu address:h12e, 12f, 131 pvmap12_0,1,3 i 2 c address h44,5f,95; cpu address:h132, 133, 135 pvmap13_0,1,3 i 2 c address h45,60,96; cpu address:h136, 137, 139 pvmap14_0,1,3 i 2 c address h46,61,97; cpu address:h13a, 13b, 13d pvmap15_0,1,3 i 2 c address h47,62,98; cpu address:h13e, 13f, 141 pvmap24_0,1,3 i 2 c address h50,6b,a1; cpu addres s:h162, 163, 165 (cpu port) pvmap25_0,1,3 i 2 c address h51,6c,a2; cpu address:h166, 167, 169 (giagabit port 1) pvmap26_0,1,3 i 2 c address h52,6d,a3; cpu address:h16a, 16b, 16d (gigabit port 2) 14.5.1 pvmode i 2 c address: h0a4, cpu address:h170 accessed by cpu, serial interface (r/w) 76543210 mac05 mma stp sm0 rpcs df sl vmod bit [0]: ? vlan mode (default = 0) - 1 tag based vlan mode - 0 port based vlan mode bit [1]: ? slow learning (default = 0) - same function as se_op mode bit 7. either bit can enable the function; both need to be turned off to disable the feature. bit [2]: ? disable dropping of frames with destination mac addresses 0180c2000001 to 0180c200000f (default = 0) - 0: drop all frames in this range - 1: disable dropping of frames in this range zl50418 data sheet 69 zarlink semiconductor inc. 14.5.2 pvroute 0 registers pvroute0 to pvroute7 allows the vlan inde x to be assigned an address of a router group. this feature is useful during ip multicast mode when data is being sent to the vlan group and no member of the group registers. by assigning a router group, the vlan group al ways has a default address to handle the multicast traffic. cpu address:h171 accessed by cpu, serial interface (r/w) bit [3]: ? disable reset pcs (default = 0) - 0: enable reset pcs. pcs fifo will be reset when received a pcs symbol error. - 1: disable reset pcs bit [4]: ? support mac address 0 (default = 0) - 0: mac address 0 is not learned. - 1: mac address 0 is learned. bit [5]: ? disable ieee multicast c ontrol frame (0180c2000000 to 0180c20000ff) to cpu in managed mode (default = 0) - 0: packet is forwarded to cpu - 1: packet is forwarded as multicast bit [6]: ? multiple mac addresses (default = 0) - 0: single mac address is assigned to cpu. registers mac0 to mac5 are used to program the cpu mac address. - 1: one block of 32 mac addresses are assigned to cpu. the block is defined in an increase way from the mac address programmed in registers mac0 to mac5. bit [7]: ? disable registers mac 5 ? 0 (cpu mac address) in comparison with ethernet frame destination mac address. when disable, unicast frames are not forward to cpu. (default = 0) -1: disable -0: enable bit [0]: ? vlan index 8?hc0 has router group and the router group is vlan index 8?h40 bit [1]: ? vlan index 8?hc1 has router group and the router group is vlan index 8?h41 bit [2]: ? vlan index 8?hc2 has router group and the router group is vlan index 8?h42 bit [3]: ? vlan index 8?hc3 has router group and the router group is vlan index 8?h43 bit [4]: ? vlan index 8?hc4 has router group and the router group is vlan index 8?h44 bit [5]: ? vlan index 8?hc5 has router group and the router group is vlan index 8?h45 bit [6]: ? vlan index 8?hc6 has router group and the router group is vlan index 8?h46 bit [7]: ? vlan index 8?hc7 has router group and the router group is vlan index 8?h47 zl50418 data sheet 70 zarlink semiconductor inc. 14.5.3 pvroute1 cpu address:h172 accessed by cpu, serial interface (r/w) 14.5.4 pvroute2 cpu address:h173 accessed by cpu, serial interface (r/w) 14.5.5 pvroute3 cpu address:h174 accessed by cpu, serial interface (r/w) bit [0]: ? vlan index 8?hc8 has router group and the router group is vlan index 8?h48 bit [1]: ? vlan index 8?hc9 has router group and the router group is vlan index 8?h48 bit [2]: ? vlan index 8?hca has router group and the router group is vlan index 8?h4a bit [3]: ? vlan index 8?hcb has router group and the router group is vlan index 8?h4b bit [4]: ? vlan index 8?hcc has router group and the router group is vlan index 8?h4c bit [5]: ? vlan index 8?hcd has router group and the router group is vlan index 8?h4d bit [6]: ? vlan index 8?hce has router group and the router group is vlan index 8?h4e bit [7]: ? vlan index 8?hcf has router grou p and the router group is vlan index 8?h4f bit [0]: ? vlan index 8?hd0 has router group and the router group is vlan index 8?h50 bit [1]: ? vlan index 8?hd1 has router group and the router group is vlan index 8?h51 bit [2]: ? vlan index 8?hd2 has router group and the router group is vlan index 8?h52 bit [3]: ? vlan index 8?hd3 has router group and the router group is vlan index 8?h53 bit [4]: ? vlan index 8?hd4 has router group and the router group is vlan index 8?h54 bit [5]: ? vlan index 8?hd5 has router group and the router group is vlan index 8?h55 bit [6]: ? vlan index 8?hd6 has router group and the router group is vlan index 8?h56 bit [7]: ? vlan index 8?hd7 has router group and the router group is vlan index 8?h57 bit [0]: ? vlan index 8?hd8 has router group and the router group is vlan index 8?h58 bit [1]: ? vlan index 8?hd9 has router group and the router group is vlan index 8?h59 bit [2]: ? vlan index 8?hda has router group and the router group is vlan index 8?h5a bit [3]: ? vlan index 8?hdb has router group and the router group is vlan index 8?h5b bit [4]: ? vlan index 8?hdc has router group and the router group is vlan index 8?h5c bit [5]: ? vlan index 8?hdd has router group and the router group is vlan index 8?h5d zl50418 data sheet 71 zarlink semiconductor inc. 14.5.6 pvroute4 cpu address:h175 accessed by cpu, serial interface (r/w) 14.5.7 pvroute5 cpu address:h176 accessed by cpu, serial interface (r/w) 14.5.8 pvroute6 cpu address:h177 accessed by cpu, serial interface (r/w) bit [6]: ? vlan index 8?hde has router gr oup and the router group is vlan index 8?h5e bit [7]: ? vlan index 8?hdf has router group and the router group is vlan index 8?h5f bit [0]: ? vlan index 8?he0 has router group and the router group is vlan index 8?h60 bit [1]: ? vlan index 8?he1 has router group and the router group is vlan index 8?h61 bit [2]: ? vlan index 8?he2 has router group and the router group is vlan index 8?h62 bit [3]: ? vlan index 8?he3 has router group and the router group is vlan index 8?h63 bit [4]: ? vlan index 8?he4 has router group and the router group is vlan index 8?h64 bit [5]: ? vlan index 8?he5 has router group and the router group is vlan index 8?h65 bit [6]: ? vlan index 8?he6 has router group and the router group is vlan index 8?h66 bit [7]: ? vlan index 8?he7 has router group and the router group is vlan index 8?h67 bit [0]: ? vlan index 8?he8 has router group and the router group is vlan index 8?h68 bit [1]: ? vlan index 8?he9 has router group and the router group is vlan index 8?h69 bit [2]: ? vlan index 8?hea has router group and the router group is vlan index 8?h6a bit [3]: ? vlan index 8?heb has router group and the router group is vlan index 8?h6b bit [4]: ? vlan index 8?hec has router group and the router group is vlan index 8?h6c bit [5]: ? vlan index 8?hed has router group and the router group is vlan index 8?h6d bit [6]: ? vlan index 8?hee has router group and the router group is vlan index 8?h6e bit [7]: ? vlan index 8?hef has router group and the router group is vlan index 8?h6f bit [0]: ? vlan index 8?hf0 has router group and the router group is vlan index 8?h70 bit [1]: ? vlan index 8?hf1 has router group and the router group is vlan index 8?h71 bit [2]: ? vlan index 8?hf2 has router group and the router group is vlan index 8?h72 zl50418 data sheet 72 zarlink semiconductor inc. 14.5.9 pvroute7 cpu address:h178 accessed by cpu, serial interface (r/w) 14.6 (group 2 address) port trunking groups trunk group 0 - up to four 10/100 ports can be selected for trunk group 0. 14.6.1 trunk0_l ? trunk group 0 low (managed mode only) cpu address:h200 accessed by cpu, serial interface (r/w) bit [7:0] port7-0 bit map of trunk 0. (default 00) 14.6.2 trunk0_m ? trunk group 0 medium (managed mode only) cpu address:h201 accessed by cpu, serial interface (r/w) bit [7:0] port15-8 bit map of trunk 0. (default 00) bit [3]: ? vlan index 8?hf3 has router group and the router group is vlan index 8?h73 bit [4]: ? vlan index 8?hf4 has router group and the router group is vlan index 8?h74 bit [5]: ? vlan index 8?hf5 has router group and the router group is vlan index 8?h75 bit [6]: ? vlan index 8?hf6 has router group and the router group is vlan index 8?h76 bit [7]: ? vlan index 8?hf7 has router group and the router group is vlan index 8?h77 bit [0]: ? vlan index 8?hf8 has router group and the router group is vlan index 8?h78 bit [1]: ? vlan index 8?hf9 has router group and the router group is vlan index 8?h79 bit [2]: ? vlan index 8?hfa has router group and the router group is vlan index 8?h7a bit [3]: ? vlan index 8?hfb has router group and the router group is vlan index 8?h7b bit [4]: ? vlan index 8?hfc has router grou p and the router group is vlan index 8?h7c bit [5]: ? vlan index 8?hfd has router grou p and the router group is vlan index 8?h7d bit [6]: ? vlan index 8?hfe has router group and the router group is vlan index 8?h7e bit [7]: ? vlan index 8?hff has router group and the router group is vlan index 8?h7f zl50418 data sheet 73 zarlink semiconductor inc. trunk0_m, and trunk0_l provid e a trunk map for trunk0. if ports 0 and 2 are to be trunked together, bit 0 and bit 2 of trunk0_l are set to 1. all others are clear at ?0? to indicate that they are not part of trunk0. up to 4 ports can be selected for trunk group 0. 14.6.3 trunk0_mode? trunk group 0 mode i 2 c address h0a5; cpu address:203 accessed by cpu, serial interface and i 2 c (r/w) 14.6.4 trunk0_hash0 ? trunk group 0 hash result 0 destination port number cpu address:h204 accessed by cpu, serial interface (r/w) bit [4:0] hash result 0 destination port number (default 00) b i t 7 b i t 0 b i t 7 b i t 0 trunk0_m trunk0_l p o r t 15 p o r t 8 p o r t 7 p o r t 0 743210 hash select port select bit [1:0]: ? port selection in unmanaged mode . input pin trunk0 enable/disable trunk group 0 in unmanaged mode. ? 00 reserved ? 01 port 0 and 1 are used for trunk0 ? 10 port 0,1 and 2 are used for trunk0 ? 11 port 0,1,2 and 3 are used for trunk0 bit [3:2] ? hash select. the hash selected is valid for trunk 0, 1 and 2. (default 00) - 00 use source and destination mac address for hashing - 01 use source mac address for hashing - 10 use destination mac address for hashing - 11 use source destination mac address and ingress physical port number for hashing zl50418 data sheet 74 zarlink semiconductor inc. 14.6.5 trunk0_hash1 ? trunk group 0 hash result 1 destination port number cpu address:h205 accessed by cpu, serial interface (r/w) bit [4:0] hash result 1 destination port number (default 01) 14.6.6 trunk0_hash2 ? trunk group 0 hash result 2 destination port number cpu address:h206 accessed by cpu, serial interface (r/w) bit [4:0] hash result 2 destination port number (default 02) 14.6.7 trunk0_hash3 ? trunk group 0 hash result 3 destination port number cpu address:h207 accessed by cpu, serial interface (r/w) bit [4:0] hash result 3 destination port number (default 03) trunk group 1 - up to four 10/100 ports can be selected for trunk group 1. 14.6.8 trunk1_l ? trunk group 1 low (managed mode only) port selection for trunk group 1. cpu address:h208 accessed by cpu, serial interface (r/w) 14.6.9 trunk1_m ? trunk group 1 medium managed mode only) cpu address:h209 accessed by cpu, serial interface (r/w) bit [7:0] port15-8 bit map of trunk 1. (default 00) 14.6.10 trunk1_mode ? trunk group 1 mode i 2 c address h0a6; cpu address:20b accessed by cpu, serial interface and i 2 c (r/w) 7 210 port select bit [1:0]: ? port selection in unmanaged mode. input pin trunk1 enable/disable trunk group 1 in unmanaged mode. -00 reserved - 01 port 4 and 5 are used for trunk1 -10 reserved - 11 port 4,5,6 and 7 are used for trunk1 zl50418 data sheet 75 zarlink semiconductor inc. 14.6.11 trunk1_hash0 ? trunk group 1 hash result 0 dest ination port number cpu address:h20c accessed by cpu, serial interface (r/w) bit [4:0] hash result 0 destination port number (default 04) 14.6.12 trunk1_hash1 ? trunk group 1 hash result 1 destination port number cpu address:h20d accessed by cpu, serial interface (r/w) bit [4:0] hash result 1 destination port number (default 05) 14.6.13 trunk1_hash2 ? trunk group 1 hash result 2 destination port number cpu address:h20e accessed by cpu, serial interface (r/w) bit [4:0] hash result 1 destination port number (default 06) 14.6.14 trunk1_hash3 ? trunk group 1 hash result 3 destination port number cpu address:h20f accessed by cpu, serial interface (r/w) bit [4:0] hash result 1 destination port number (default 07) trunk group 2 14.6.15 trunk2_mode ? trunk grou p 2 mode (gigabit ports 1 and 2) cpu address:210 accessed by cpu, serial interface (r/w) 76 430 ring/trunk mode bit [3:0] - reserved bit [6:4] - 000 normal - 001 trunk mode. enable trunk group for gigabit port 1 and 2 in managed mode. in unmanaged mode trunk 2 is enable/disable using input pin trunk2. - 010 single ring with g1 - 100 single ring with g2 - 111 dual ring mode zl50418 data sheet 76 zarlink semiconductor inc. 14.6.16 trunk2_hash0 ? trunk group 2 hash result 0 destination port number cpu address:h211 accessed by cpu, serial interface (r/w) bit [4:0] hash result 0 destination port number (default 0x19) 0x19 = gigabit port 1 0x1a = gigabit port 2 14.6.17 trunk2_hash1 ? trunk group 2 hash result 1 destination port number cpu address:h211 accessed by cpu, serial interface (r/w) bit [4:0] hash result 1 destination port number (default 0x1a) 0x19 = gigabit port 1 0x1a = gigabit port 2 14.6.18 multicast hash registers multicast hash registers are used to distribute multicast tr affic. 16 registers are used to form a 4-entry array; each entry has 27 bits, with each bit representing one port. any port not belonging to a trunk group should be programmed with 1. ports belonging to the same trunk group should only have a single port set to ?1? per entry. the port set to ?1? is picked to transmit the multicast frame when the hash value is met. 14.6.18.1 multicast_hash0-0 ? multicast hash result 0 mask byte 0 cpu address:h220 accessed by cpu, serial interface (r/w) bit [7:0] default ff) hash value =0 hash0_ 3 hash0_2 hash0_1 hash0_0 hash value =1 hash1_ 3 hash1_2 hash1_1 hash1_0 hash value =2 hash2_ 3 hash2_2 hash2_1 hash2_0 hash value =3 hash3_ 3 hash3_2 hash3_1 hash3_0 p o r t 2 6 p o r t 24 c p u p o r t 15 p o r t 8 p o r t 7 p o r t 0 zl50418 data sheet 77 zarlink semiconductor inc. 14.6.18.2 multicast_hash0-1 ? multicast hash result 0 mask byte 1 cpu address:h221 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.3 multicast_hash0-3 ? multicast hash result 0 mask byte 3 cpu address:h223 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.4 multicast_hash1-0 ? multicast hash result 1 mask byte 0 cpu address:h224 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.5 multicast_hash1-1 ? multicast hash result 1 mask byte 1 cpu address:h225 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.6 multicast_hash1-3 ? multicast hash result 1 mask byte 3 cpu address:h227 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.7 multicast_hash2-0 ? multicast hash result 2 mask byte 0 cpu address:h228 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.8 multicast_hash2-1 ? multicast hash result 2 mask byte 1 cpu address:h229 accessed by cpu, serial interface (r/w) bit [7:0] (default ff) zl50418 data sheet 78 zarlink semiconductor inc. 14.6.18.9 multicast_hash2-3 ? multicast hash result 2 mask byte 3 cpu address:h22b accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.10 multicast_hash3-0 ? multicast hash result 3 mask byte 0 cpu address:h22c accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.11 multicast_hash3-1 ? multicast hash result 3 mask byte 1 cpu address:h22d accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.6.18.12 multicast_hash3-3 ? multicast hash result 3 mask byte 3 cpu address:h22f accessed by cpu, serial interface (r/w) bit [7:0] (default ff) 14.7 (group 3 address) cpu port configuration group mac5 to mac0 registers form the cpu mac address. when a packet with destination mac address match mac [5:0], the packet is fo rwarded to the cpu. 14.7.1 mac0 ? cpu mac address byte 0 cpu address:h300 accessed by cpu bit [7:0] byte 0 of the cpu mac address. (default 00) 14.7.2 mac1 ? cpu mac address byte 1 cpu address:h301 accessed by cpu bit [7:0] byte 1 of the cpu mac address. (default 00) 5 0 (mc bit) mac5 mac4 mac3 mac2 mac1 mac0 zl50418 data sheet 79 zarlink semiconductor inc. 14.7.3 mac2 ? cpu mac address byte 2 cpu address:h302 accessed by cpu bit [7:0] byte 2 of the cpu mac address. (default 00) 14.7.4 mac3 ? cpu mac address byte 3 cpu address:h303 accessed by cpu bit [7:0] byte 3 of the cpu mac address. (default 00) 14.7.5 mac4 ? cpu mac address byte 4 cpu address:h304 accessed by cpu bit [7:0] byte 4 of the cpu mac address. (default 00) 14.7.6 mac5 ? cpu mac address byte 5 cpu address:h305 accessed by cpu bit [7:0] byte 5 of the cpu mac address. (default 00). 14.7.7 int_mask0 ? interrupt mask 0 cpu address:h306 accessed by cpu, serial interface (r/w) the cpu can dynamically mask the interrupt when it is busy and doesn?t want to be interrupted. ( default 0xff) bit [7:0] mask - 1: mask the interrupt - 0: unmask the interrupt (enable interrupt) bit [0]: ? cpu frame interrupt. cpu frame buffer has data for cpu to read bit [1]: ? control command 1 interrupt. control command frame buffer1 has data for cpu to read bit [2]: ? control command 2 interrupt. control command frame buffer2 has data for cpu to read bit [7:3]: ? reserved zl50418 data sheet 80 zarlink semiconductor inc. 14.7.8 intp_mask0 ? interrupt mask for mac port 0,1 cpu address:h310 accessed by cpu, serial interface (r/w) the cpu can dynamically mask the interrupt when it is busy and doesn?t want to be interrupted ( default 0xff) - 1: mask the interrupt - 0: unmask the interrupt bit [0]: port 0 statistic counter wrap around interrupt mask . an interrupt is generated when a statistic counter wraps around. refer to hardware statis tic counter for in terrupt sources. bit [1]: port 0 link change mask bit [4]: port 1 statistic counter wrap around interrupt mask. refer to hardware statistic counter fo r interrupt sources. bit [5]: port 1 link change mask 14.7.9 intp_mask1 ? interrupt mask for mac port 2,3 cpu address:h311 accessed by cpu, serial interface (r/w) 14.7.10 intp_mask2 ? interrupt mask for mac port 4,5 cpu address:h312 accessed by cpu, serial interface (r/w) 14.7.11 intp_mask3 ? interrupt mask for mac port 6,7 cpu address:h313 accessed by cpu, serial interface (r/w) 14.7.12 intp_mask4 ? interrupt mask for mac port 8,9 cpu address:h314 accessed by cpu, serial interface (r/w) 14.7.13 intp_mask5 ? interrupt mask for mac port 10,11 cpu address:h315 accessed by cpu, serial interface (r/w) 14.7.14 intp_mask6 ? interrupt mask for mac port 12,13 cpu address:h316 accessed by cpu, serial interface (r/w) 76 543210 p1 p0 zl50418 data sheet 81 zarlink semiconductor inc. 14.7.15 intp_mask7 ? interrupt mask for mac port 14,15 cpu address:h317 accessed by cpu, serial interface (r/w) 14.7.16 intp_mask12 ? interrupt mask for mac port g1,g2 cpu address:h31c accessed by cpu, serial interface (r/w) 14.7.17 rqs ? receive queue select cpu address:h323 accessed by cpu, serial interface (r/w) select which receive queue is used. bit [0]: select queue 0. if se t to one, this queue may be scheduled to cpu port. if se t to zero, this queue will be blocked. if multiple queues are select ed, a strict priority will be applied. q3> q2> q1> q0. same applies to bits [3:1]. see qos application no te for more information. bit [1]: select queue 1 bit [2]: select queue 2 bit [3]: select queue 3 note: strip priority applies between different selected queues (q3>q2>q1>q0) bit [4]: enable flush queue 0 bit [5]: enable flush queue 1 bit [6]: enable flush queue 2 bit [7]: enable flush queue 3 when flush (drop frames) is enable, it starts when queue is too long or entry is too old. a queue is too long when it reaches wred thresholds. queue 0 is not subject to early drop. packets in queue 0 are dropped only when the queue is too old. an entry is too old when it is older than the time programmed in th e register tx_age [5:0]. cpu can dynamically program this register reading register rqss [7:4]. 14.7.18 rqss ? receive queue status cpu address:h324 accessed by cpu, serial interface (ro) 76543 21 0 fq3 fq2 fq1 fq0 sq3 sq2 sq1 sq0 7543 0 lq3 lq2 lq1 lq0 neq3 neq2 neq1 neq0 zl50418 data sheet 82 zarlink semiconductor inc. cpu receive queue status - bit [3:0]: queue 3 to 0 not empty - bit [4]: head of line entry for queue 0 is valid for too long. cpu queue 0 has no wred threshold. - bit [7:5]: head of line entry for queue 3 to 1 is valid for too long or queue length is longer than wred threshold. tx_age ? tx queue aging timer i 2 c address: h07;cpu address:h324 accessed by cpu, serial interface (rw) - bit [5:0]: unit of 100ms (default 8) disable transmission queue agi ng if value is zero. aging timer for all ports and queues. this register must be set to 0 for ?no packet loss flow control test?. 14.8 (group 4 address) search engine group 14.8.1 agetime_low ? mac address aging time low i 2 c address h0a8; cpu address:h400 accessed by cpu, serial interface and i 2 c (r/w) the zl50418 removes the mac address from the data base and sends a delete mac address control command to the cpu. mac address aging is enable/disable by boot strap tstout9. bit [7:0] low byte of the mac address aging timer. 14.8.2 agetime_high ?m ac address aging time high i 2 c address h0a9; cpu address h401 accessed by cpu, serial interface and i 2 c (r/w) bit [7:0]: high byte of the mac address aging timer. the default setting provide 300 seconds aging time. aging time is based on the following equation: {agetime_time,agetime_low} x (# of mac entries in the memory x100sec). number of mac entries = 32 k when 1 mb is used per bank. number of entries = 64 k when 2 mb is used per bank. 76 5 0 tx queue agent zl50418 data sheet 83 zarlink semiconductor inc. 14.8.3 +scan ? scan cont rol register (default 00) cpu address h404 accessed by cpu (r/w) scan is used when fast learning is enabled (se_opmode bit 0). it is used for setting up the report rate for newly learned mac addresses to the cpu. examples: r= 0, ratio = 0: all rounds are used for aging. never scan for new mac addresses. r= 0, ratio = 1: aging and scanning in every other aging round r= 1, ratio = 7: in eight rounds, one is us ed for scanning and seven are used for aging r= 0, ratio = 7: in eight rounds, one is used for aging and seven are used for scanning 14.9 (group 5 address) buffer control/qos group 14.9.1 fcbat ? fcb aging timer i 2 c address h0aa; cpu address:h500 14.9.2 qosc ? qos control i 2 c address h0ab; cpu address:h501 accessed by cpu, serial interface and i 2 c (r/w) 76 0 rratio bit [6:0]: ? ratio between database scanning and aging round (default 00) bit [7]: ? reverse the ratio between scanning round and aging round (default 0) 70 fcbat bit [7:0]: ? fcb aging time. unit of 1ms. (default ff) ? this is for buffer aging control. it is used to configure the buffer aging time. this function can be enabled/dis abled through bootstrap pin. it is not suggested to use this function for normal operation. 76 5 43 10 tos-d tos-p pmcq vf1c l bit [0]: ? qos frame lost is ok. priority will be available for flow control enabled source only when this bit is set (default 0) zl50418 data sheet 84 zarlink semiconductor inc. 14.9.3 fcr ? flooding control register i 2 c address h0ac; cpu address:h502 accessed by cpu, serial interface and i 2 c (r/w) bit [4]: ? per vlan multicast flow control (default 0) - 0 ? disable - 1 ? enable bit [5]: ? select processor multicast queue size - 0 = 16 entries - 1 = 64 entries bit [6]: ? select tos bits for priority (default 0) - 0 ? use tos [4:2] bits to map the transmit priority - 1 ? use tos [7:5] bits to map the transmit priority bit [7]: ? select tos bits for drop priority(default 0) - 0 ? use tos [4:2] bits to map the drop priority - 1 ? use tos [7:5] bits to map the drop priority 76 43 0 tos timebase u2mr bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of time base defined in bits [6:4]. this is used to limit the amount of flooding traffic. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to disabl e this function, program u2mr to 0. (default = 8) bit [6:4]: ? time base: (default = 000) -000 = 100us -001 = 200us -010 = 400us - 011 = 800 us -100 = 1.6ms -101 = 3.2ms -110 = 6.4ms - 111 = 100 us , same as 000. bit [7]: ? select vlan tag or tos (ip packets) to be preferentially picked to map transmit priority and drop priority ( default = 0 ). - 0 ? select vlan tag priority field over tos - 1 ? select tos over vl an tag priority field zl50418 data sheet 85 zarlink semiconductor inc. 14.9.4 avpml ? vlan tag priority map i 2 c address h0ad; cpu address:h503 accessed by cpu, serial interface and i 2 c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan ta g priorities to map into eight internal level transmit priorities. under the internal tr ansmit priority, seven is the highest priority where as zero is the lowest. this feature allows the user the flexibility of redefining the vlan priority field. for ex ample, programming a va lue of 7 into bit 2:0 of the avpml register would map packet vlan priority 0 into internal transmit priority 7. the new priority is used inside the zl50418. when the packet goes out it carries the original priority. 14.9.5 avpmm ? vlan priority map i 2 c address h0ae, cpu address:h504 accessed by cpu, serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 14.9.6 avpmh ? vlan priority map i 2 c address h0af, cpu address:h505 accessed by cpu, serial interface and i 2 c (r/w) 76 5 32 0 vp2 vp1 vp0 bit [2:0]: priority when the vlan tag priority field is 0 (default 0) bit [5:3]: priority when the vlan tag priority field is 1 ( default 0) bit [7:6]: priority when the vlan tag priority field is 2 (default 0) 7 6 43 10 vp5 vp4 vp3 vp2 bit [0]: priority when the vlan tag priority field is 2 (default 0) bit [3:1]: priority when the vlan tag priority field is 3 (default 0) bit [6:4]: priority when the vlan tag priority field is 4 (default 0) bit [7]: priority when the vlan tag priority field is 5 (default 0) 754210 vp7 vp6 vp5 zl50418 data sheet 86 zarlink semiconductor inc. map vlan priority into eight level transmit priorities: 14.9.7 tospml ? tos priority map i 2 c address h0b0, cpu address:h506 accessed by cpu, serial interface and i 2 c (r/w) map tos field in ip packet into eight level transmit priorities 14.9.8 tospmm ? tos priority map i 2 c address h0b1, cpu address:h507 accessed by cpu, serial interface and i 2 c (r/w) map tos field in ip packet into eight level transmit priorities 14.9.9 tospmh ? tos priority map i 2 c address h0b2, cpu address:h508 accessed by cpu, serial interface and i 2 c (r/w) bit [1:0]: priority when the vlan tag priority field is 5 (default 0) bit [4:2]: priority when the vlan tag priority field is 6 (default 0) bit [7:5]: priority when the vlan tag priority field is 7 (default 0) 76 5 32 0 tp2 tp1 tp0 bit [2:0]: priority when the tos field is 0 (default 0) bit [5:3]: priority when the tos field is 1 (default 0) bit [7:6]: priority when the tos field is 2 (default 0) 7 6 43 10 tp5 tp4 tp3 tp2 bit [0]: priority when the tos field is 2 (default 0) bit [3:1]: priority when the tos field is 3 (default 0) bit [6:4]: priority when the tos field is 4 (default 0) bit [7]: priority when the tos field is 5 (default 0) 754210 tp7 tp6 tp5 zl50418 data sheet 87 zarlink semiconductor inc. map tos field in ip packet into eight level transmit priorities: 14.9.10 avdm ? vlan discard map i 2 c address h0b3, cpu address:h509 accessed by cpu, serial interface and i 2 c (r/w) map vlan priority into frame discard when low priority buffer usage is above threshold 14.9.11 tosdml ? tos discard map i 2 c address h0b4, cpu address:h50a accessed by cpu, serial interface and i 2 c (r/w) map tos into frame discard when low priority buffer usage is above threshold bit [1:0]: priority when the tos field is 5 (default 0) bit [4:2]: priority when the tos field is 6 (default 0) bit [7:5]: priority when the tos field is 7 (default 0) 7 6543210 fdv7 fdv6 fdv5 fdv4 fdv3 fdv2 fdv1 fdv0 bit [0]: frame drop priority when vlan tag priority field is 0 (default 0) bit [1]: frame drop priority when vlan tag priority field is 1 (default 0) bit [2]: frame drop priority when vlan tag priority field is 2 (default 0) bit [3]: frame drop priority when vlan tag priority field is 3 (default 0) bit [4]: frame drop priority when vlan tag priority field is 4 (default 0) bit [5]: frame drop priority when vlan tag priority field is 5 (default 0) bit [6]: frame drop priority when vlan tag priority field is 6 (default 0) bit [7]: frame drop priority when vlan tag priority field is 7 (default 0) 7 65432 10 fdt7 fdt6 fdt5 fdt4 fdt3 fdt2 fdt1 fdt0 bit [0]: frame drop priority when tos field is 0 (default 0) bit [1]: frame drop priority when tos field is 1 (default 0) bit [2]: frame drop priority when tos field is 2 (default 0) bit [3]: frame drop priority when tos field is 3 (default 0) bit [4]: frame drop priority when tos field is 4 (default 0) zl50418 data sheet 88 zarlink semiconductor inc. 14.9.12 bmrc - broadcas t/multicast rate control i 2 c address h0b5, cpu address:h50b) accessed by cpu, serial interface and i 2 c (r/w) this broadcast and multicast rate defi nes for each port, the number of packets allowed to be forwarded within a specified time. once the packet rate is reached, packets will be dropped. to turn off th e rate limit, program the field to 0. time base is based on register fcr [6:4] 14.9.13 ucc ? unicast congestion control i 2 c address h0b6, cpu address: 50c accessed by cpu, serial interface and i 2 c (r/w) 14.9.14 mcc ? multicast congestion control i 2 c address h0b7, cpu address: 50d accessed by cpu, serial interface and i 2 c (r/w) bit [5]: frame drop priority when tos field is 5 (default 0) bit [6]: frame drop priority when tos field is 6 (default 0) bit [7]: frame drop priority when tos field is 7 (default 0) 7430 broadcast rate multicast rate bit [3:0]: multicast rate control. number of multicast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) . bit [7:4]: broadcast rate control. number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) 70 unicast congest threshold bit [7:0]: number of frame count. used for be st effort dropping at b% when destination port?s best effort queue reaches ucc threshold and shared pool is all in use. granularity 1 frame. (default: h10 for 2 mb/bank or h08 for 1 mb/bank) 754 0 fc reaction period multicast congest threshold zl50418 data sheet 89 zarlink semiconductor inc. 14.9.15 pr100 ? port reservation for 10/100 ports i 2 c address h0b8, cpu address 50e accessed by cpu, serial interface and i 2 c (r/w) 14.9.16 prg ? port reservation for giga ports i 2 c address h0b9, cpu address 50f accessed by cpu, serial interface and i 2 c (r/w) bit [4:0]: in multiples of two frames (granula rity). used for triggering mc flow control when destination port?s multicast best effort queue reaches mcc threshold.(default 0x10) bit [7:5]: flow control reaction peri od (default 2) granularity 4 usec. 7430 buffer low threshold sp buffer reservation bit [3:0]: per source port buffer reservation. define the space in the fdb reserved for each 10/100 port and cpu. expressed in multiples of 4 packets. for each packet 1536 bytes are reserved in the memory. bits [7:4]: expressed in multiples of 4 packets. threshold for dropping all best effort frames when destination port best efforts queues reaches ucc threshold, shared pool is all used and source port reservation is at or below the pr100[7:4] level. also the threshol d for initiating uc flow control. ? default: - h36 for 16+2 configuration with memory 2 mb/bank; - h24 for 16+2 configuration with 1 mb/bank; 7430 buffer low threshold sp buffer reservation bit [3:0]: per source port buffer reservation. define the space in the fdb reserved for each gigabit port. expressed in multiples of 16 packets. for each packet 1536 bytes are reserved in the memory. bits [7:4]: expressed in multip les of 16 packets. threshold for dropping all best effort frames when destination port best effort queues reach ucc threshold, shared pool is all used and source port reservation is at or below the prg[7:4] level. also the threshol d for initiating uc flow control. ? default: - h58 for memory 2 mb/bank; - h35 for 1 mb/bank; zl50418 data sheet 90 zarlink semiconductor inc. 14.9.17 sfcb ? share fcb size i 2 c address h0ba), cpu address 510 accessed by cpu, serial interface and i 2 c (r/w) 14.9.18 c2rs ? class 2 reserve size i 2 c address h0bb, cpu address 511 accessed by cpu, serial interface and i 2 c (r/w) buffer reservation for class 2 (third lowest priority). granularity 1. (default 0) 14.9.19 c3rs ? class 3 reserve size i 2 c address h0bc, cpu address 512 accessed by cpu, serial interface and i 2 c (r/w) buffer reservation for class 3. granularity 1. (default 0) 14.9.20 c4rs ? class 4 reserve size i 2 c address h0bd, cpu address 513 accessed by cpu, serial interface and i 2 c (r/w) buffer reservation for class 4. granularity 1. (default 0) 70 shared pool buffer size bits [7:0]: expressed in multiples of 4 packets. buffer reservation for shared pool. ? default: - h64 for 16+2 configuration with memory of 2 mb/bank; - h14 for 16+2 configuration with memory of 1 mb/bank; 70 class 2 fcb reservation 70 class 3 fcb reservation 70 class 4 fcb reservation zl50418 data sheet 91 zarlink semiconductor inc. 14.9.21 c5rs ? class 5 reserve size i 2 c address h0be; cpu address 514 accessed by cpu, serial interface and i 2 c (r/w) buffer reservation for class 5. granularity 1. (default 0) 14.9.22 c6rs ? class 6 reserve size i 2 c address h0bf; cpu address 515 accessed by cpu, serial interface and i 2 c (r/w) buffer reservation for class 6 (seco nd highest priority). granularity 1. (default 0) 14.9.23 c7rs ? class 7 reserve size i 2 c address h0c0; cpu address 516 accessed by cpu, serial interface and i 2 c (r/w) buffer reservation for class 7 (highest priority). granularity 1. (default 0) 14.9.24 qoscn - classes byte limit set 0 accessed by cpu; serial interface and i 2 c (r/w): ? c ? qosc00 ? byte_c01 (i 2 c address h0c1, cpu address 517) ? b ? qosc01 ? byte_c02 (i 2 c address h0c2, cpu address 518) ? a ? qosc02 ? byte_c03 (i 2 c address h0c3, cpu address 519) qosc00 through qosc02 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme described in chapter 7. there are four such sets of values a-c specified in classes byte limit set 0, 1, 2, and 3. for cpu port a-c values are defined using register cpuqosc1, 2 and 3. each 10/ 100 port can choose one of the four byte limit sets as specified by the qos select field located in bits 5 to 4 of the ecr2n register. the values a-c are per-q ueue byte thresholds for random early drop. qosc02 represents a, and qosc00 represents c. granularity when delay bound is used: qosc02: 128 byte s, qosc01: 256 bytes, qosc00: 512 bytes. granularity when wfq is used: qosc02: 512 bytes, qosc01: 512 bytes, qosc00: 512 bytes. 70 class 5 fcb reservation 70 class 6 fcb reservation 70 class 7 fcb reservation zl50418 data sheet 92 zarlink semiconductor inc. 14.9.25 classes byte limit set 1 accessed by cpu, serial interface and i 2 c (r/w): ? c - qosc03 ? byte_c11 (i 2 c address h0c4, cpu address 51a) ? b - qosc04 ? byte_c12 (i 2 c address h0c5, cpu address 51b) ? a - qosc05 ? byte_c13 (i 2 c address h0c6, cpu address 51c) qosc03 through qosc05 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme. granularity when delay bound is used: qosc05: 128 byte s, qosc04: 256 bytes, qosc03: 512 bytes. granularity when wfq is used: qosc05: 512 bytes, qosc04: 512 bytes, qosc03: 512 bytes. 14.9.26 classes byte limit set 2 accessed by cpu and serial interface (r/w): ? c - qosc06 ? byte_c21 (cpu address 51d) ? b - qosc07 ? byte_c22 (cpu address 51e) ? a - qosc08 ? byte_c23 (cpu address 51f) qosc06 through qosc08 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme. granularity when delay bound is used: qosc08: 128 bytes, qosc07: 256 byte s, qosc06: 512 bytes. granularity when wfq is used: qosc08: 512 bytes, qosc07: 512 bytes, qosc06: 512 bytes 14.9.27 classes byte limit set 3 accessed by cpu and serial interface (r/w): ? c - qosc09 ? byte_c31 (cpu address 520) ? b - qosc10 ? byte_c32 (cpu address 521) ? a - qosc11 ? byte_c33 (cpu address 522) qosc09 through qosc011 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme. granularity when delay bound is used: qosc11: 12 8 bytes, qosc10: 256 bytes, qosc09: 512 bytes. granularity when wfq is used: qosc11: 512 by tes, qosc10: 512 bytes, qosc09: 512 bytes 14.9.28 classes byte limit giga port 1 accessed by cpu, serial interface and i 2 c (r/w): ? f - qosc12 ? byte_c2_g1 (i 2 c address h0c7, cpu address 523) ? e - qosc13 ? byte_c3_g1 (i 2 c address h0c8, cpu address 524) ? d - qosc14 ? byte_c4_g1 (i 2 c address h0c9, cpu address 525) ? c -qosc15 ? byte_c5_g1 (i 2 c address h0ca, cpu address 526) ? b - qosc16 ? byte_c6_g1 (i 2 c address h0cb, cpu address 527) ? a - qosc17 ? byte_c7_g1 (i 2 c address h0cc, cpu address 528) qosc12 through qosc17 represent the values a-f for gigabit port 1. they are per-queue byte thresholds for random early drop. qosc17 represents a and qosc12 represents f. zl50418 data sheet 93 zarlink semiconductor inc. granularity when delay bound is used: qosc17 and qosc16: 256 bytes, qosc15 and qosc14: 512 bytes, qosc13 and qosc12: 1024 bytes. granularity when wfq is used: qosc17 to qosc12: 1024 bytes 14.9.29 classes byte limit giga port 2 accessed by cpu, serial interface and i 2 c (r/w) ? f - qosc18 ? byte_c2_g2 (i 2 c address h0cd, cpu address 529) ? e - qosc19 ? byte_c3_g2 (i 2 c address h0ce, cpu address 52a) ? d - qosc20 ? byte_c4_g2 (i 2 c address h0cf, cpu address 52b) ? c - qosc21 ? byte_c5_g2 (i 2 c address h0d0, cpu address 52c) ? b - qosc22 ? byte_c6_g2 (i 2 c address h0d1, cpu address 52d) ? a - qosc23 ? byte_c7_g2 (i 2 c address h0d2, cpu address 52e) qosc12 through qosc17 represent the values a-f for gigabit port 2. they are per-queue byte thresholds for random early drop. qosc17 represents a, and qosc12 represents f. granularity when delay bound is used: qosc17 and qosc16: 256 bytes, qosc15 and qosc14: 512 bytes, qosc13 and qosc12: 1024 bytes. granularity when wfq is used: qosc17 to qosc12: 1024 bytes 14.9.30 classes wfq credit set 0 accessed by cpu and serial interface ? w0 - qosc24[5:0] ? credit_c00 (cpu address 52f) ? w1 - qosc25[5:0] ? credit_c01 (cpu address 530) ? w2 - qosc26[5:0] ? credit_c02 (cpu address 531) ? w3 - qosc27[5:0] ? credit_c03 (cpu address 532) qosc24 through qosc27 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc27 corresponds to w3 and qosc24 corresponds to w0. qosc24[7:6]: priority service type for the ports se lect this parameter set. option 1 to option 4. qosc25[7]: priority service allow flow contro l for the ports select this parameter set. qosc25[6]: flow control pause best effort traffic only both flow control allow and flow control best effort only can take effect only the priority type is wfq. 14.9.31 classes wfq credit set 1 accessed by cpu and serial interface ? w0 - qosc28[5:0] ? credit_c10 (cpu address 533) ? w1 - qosc29[5:0] ? credit_c11 (cpu address 534) ? w2 - qosc30[5:0] ? credit_c12 (cpu address 535) ? w3 - qosc31[5:0] ? credit_c13 (cpu address 536) qosc28 through qosc31 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc31 corresponds to w3 and qosc28 corresponds to w0. zl50418 data sheet 94 zarlink semiconductor inc. qosc28[7:6]: priority service type for the ports se lect this parameter set. option 1 to option 4. qosc29[7]: priority service allow flow contro l for the ports select this parameter set. qosc29[6]: flow control pause best effort traffic only 14.9.32 classes wfq credit set 2 accessed by cpu and serial interface ? w0 - qosc32[5:0] ? credit_c20 (cpu address 537) ? w1 - qosc33[5:0] ? credit_c21 (cpu address 538) ? w2 - qosc34[5:0] ? credit_c22 (cpu address 539) ? w3 - qosc35[5:0] ? credit_c23 (cpu address 53a) qosc35 through qosc32 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1 and their sum must be 64. qosc35 corresponds to w3, and qosc32 corresponds to w0. qosc32[7:6]: priority service type for the ports se lect this parameter set. option 1 to option 4. qosc33[7]: priority service allow flow contro l for the ports select this parameter set. qosc33[6]: flow control pause for best effort traffic only 14.9.33 classes wfq credit set 3 accessed by cpu and serial interface ? w0 - qosc36[5:0] ? credit_c30 (cpu address 53b) ? w1 - qosc37[5:0] ? credit_c31 (cpu address 53c) ? w2 - qosc38[5:0] ? credit_c32 (cpu address 53d) ? w3 - qosc39[5:0] ? credit_c33 (cpu address 53e) qosc39 through qosc36 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1 and their sum must be 64. qosc39 corresponds to w3, and qosc36 corresponds to w0. qosc36[7:6]: priority service type for the ports se lect this parameter set. option 1 to option 4. qosc37[7]: priority service allow flow contro l for the ports select this parameter set. qosc37[6]: flow control pause best effort traffic only 14.9.34 classes wfq credit port g1 accessed by cpu and serial interface ? w0 - qosc40[5:0] - credit_c0_g1(cpu address 53f) [7:6]: priority service type. option 1 to 4. ? w1 - qosc41[5:0] ? credit_c1_g1 (cpu address 540) [7]: priority service allow flow control for the ports select this parameter set. [6]: flow control pause best effort traffic only ? w2 - qosc42[5:0] ? credit_c2_g1 (cpu address 541) ? w3 - qosc43[5:0] ? credit_c3_g1 (cpu address 542) ? w4 - qosc44[5:0] ? credit_c4_g1 (cpu address 543) zl50418 data sheet 95 zarlink semiconductor inc. ? w5 - qosc45[5:0] ? credit_c5_g1 (cpu address 544) ? w6 - qosc46[5:0] ? credit_c6_g1 (cpu address 545) ? w7 - qosc47[5:0] ? credit_c7_g1 (cpu address 546) qosc40 through qosc47 represents the set of wfq para meters for gigabit port 24. the granularity of the numbers is 1 and their sum must be 64. qosc47 corresponds to w7, and qosc40 corresponds to w0. 14.9.35 classes wfq credit port g2 accessed by cpu and serial interface ? w0 - qosc48[5:0] ? credit_c0_g2(cpu address 547) [7:6]: priority service type. option 1 to 4 ? w1 - qosc49[5:0] ? credit_c1_g2(cpu address 548) [7]: priority service allow flow control for the ports select this parameter set. [6]: flow control pause best effort traffic only ? w2 - qosc50[5:0] ? credit_c2_g2(cpu address 549) ? w3 - qosc51[5:0] ? credit_c3_g2(cpu address 54a) ? w4 - qosc52[5:0] ? credit_c4_g2(cpu address 54b) ? w5 - qosc53[5:0] ? credit_c5_g2(cpu address 54c) ? w6 - qosc54[5:0] ? credit_c6_g2(cpu address 54d) ? w7 - qosc55[5:0] ? credit_c7_g2(cpu address 54e) qosc48 through qosc55 represents the set of wfq parame ters for gigabit port 2. the granularity of the numbers is 1 and their sum must be 64. qosc55 corresponds to w7 and qosc48 corresponds to w0. 14.9.36 class 6 shaper control port g1 accessed by cpu and serial interface qosc56[5:0] ? token_rate_g1 (cpu address 54f). progra ms de average rate for gigabit port 1. when equal to 0, shaper is disable. granularity is 1. qosc57[7:0] ? token_limit_g1 (cpu address 550). programs the maximum counter for gigabit port 1. granularity is 16 bytes. shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). shaper is limited to gigabit ports and queue p6 when it is in strict priority. qosc41 programs the peak rate for gigabit port 1. see programming qos registers application note for more information 14.9.37 class 6 shaper control port g2 accessed by cpu and serial interface qosc58[5:0] ? token_rate_g2 (cpu address 551). program s de average rate for gigabit port 2. when equal to 0, shaper is disable. granularity is 1. qosc59[7:0] ? token_limit_g2 (cpu address 552). programs the maximum counter for gigabit port 2. granularity is 16 bytes. shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). shaper is limited to gigabit ports and queue p6 when it is in strict priority. qosc49 programs the peak rate for gigabit port 2. see programming qos register application note for more information. zl50418 data sheet 96 zarlink semiconductor inc. 14.9.38 rdrc0 ? wred rate control 0 i 2 c address 0fb, cpu address 553 accessed by cpu, serial interface and i c c (r/w) 14.9.39 rdrc1 ? wred rate control 1 i 2 c address 0fc, cpu address 554 accessed by cpu, serial interface and i 2 c (r/w) 14.9.40 user defined logical ports and well known ports the zl50418 supports classifying packet priority through la yer 4 logical port information. it can be setup by 8 well known ports, 8 user defined logical ports and 1 user defined range. the 8 well known ports supported are: ?0:23 ? 1:512 ? 2:6000 ? 3:443 ?4:111 ? 5:22555 ?6:22 ? 7:554 their respective priority can be programmed via well_know n_port [7:0] priority register. well_known_port_ enable can individually turn on/off each well known port if desired. similarly, the user defined logical port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. the 8 user logical ports can be programmed via user_port 0-7 registers. two registers are required to be programmed for the logical port number. the respective priority can be 7430 x rate y rate bits [7:4]: corresponds to the frame drop percentage x% for wred. granularity 6.25%. bits[3:0]: corresponds to the frame drop percentage y% for wred. granularity 6.25%. see programming qos registers applic ation note for more information. 7430 z rate b rate bits [7:4]: corresponds to the frame drop percentage z% for wred. granularity 6.25%. bits[3:0]: corresponds to the best effort frame drop percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. granularity 6.25%. see programming qos registers applic ation note for more information. zl50418 data sheet 97 zarlink semiconductor inc. programmed to the user_port [7:0] priority register. the port priority can be individually enabled/disabled via user_port_enable register. the user defined range provides a range of logical port numbers with the same priority level. programming is similar to the user defined logical port. instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {rhighh, rhighl} and {rlowh, rlowl} respectively. if the value in the upper limit is smaller or equal to the lower limit, th e function is disabled. any ip packet with a logical port that is less than the upper limit and more than the lower limit will use the priori ty specified in rpriority. 14.9.40.1 user_port0_(0~7) ? user define logical port (0~7) user_port_0 - i 2 c address h0d6 + 0de; cpu address 580(low) + 581(high) user_port_1 - i 2 c address h0d7 + 0df; cpu address 582 + 583 user_port_2 - i 2 c address h0d8 + 0e0; cpu address 584 + 585 user_port_3 - i 2 c address h0d9 + 0e1; cpu address 586 + 587 user_port_4 - i 2 c address h0da + 0e2; cpu address 588 + 589 user_port_5 - i 2 c address h0db + 0e3; cpu address 58a + 58b user_port_6 - i 2 c address h0dc + 0e4; cpu address 58c + 58d user_port_7 - i 2 c address h0dd + 0e5; cpu address 58e + 58f accessed by cpu, serial interface and i 2 c (r/w) (default 00) this register is duplicated eight times fr om port 0 through port 7 and allows the cpu to define eight separate ports. 14.9.40.2 user_port_[1:0]_priority - u ser d efine l ogic p ort 1 and 0 p riority i 2 c address h0e6, cpu address 590 accessed by cpu, serial interface and i 2 c (r/w) the chip allows the cpu to define the priority. 70 tcp/udp logic port low 70 tcp/udp logic port high 7543 10 priority 1 drop priority 0 drop bits [3:0]: priority setting, transmission + dropping, for logic port 0 bits [7:4]: priority setting, transmission + dropping, for logic port 1 (default 00) zl50418 data sheet 98 zarlink semiconductor inc. 14.9.40.3 user_port_[3:2]_priority - u ser d efine l ogic p ort 3 and 2 p riority i 2 c address h0e7, cpu address 591 accessed by cpu, serial interface and i 2 c (r/w) 14.9.40.4 user_port_[5:4]_priority - u ser d efine l ogic p ort 5 and 4 p riority i 2 c address h0e8, cpu address 592 accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.5 user_port_[7:6]_priority - u ser d efine l ogic p ort 7 and 6 p riority i 2 c address h0e9, cpu address 593 accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.6 user_port_enable[7:0] ? u ser d efine l ogic 7 to 0 p ort e nables i 2 c address h0ea, cpu address 594 accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.7 well_known_port[1:0] priority- w ell k nown l ogic p ort 1 and 0 p riority i 2 c address h0eb, cpu address 595 accessed by cpu, serial interface and i 2 c (r/w) priority 0 - well known port 23 for telnet applications. 754310 priority 3 drop priority 2 drop 754310 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 754310 priority 1 drop priority 0 drop zl50418 data sheet 99 zarlink semiconductor inc. priority 1 - well known port 512 for tcp/udp. (default 00) 14.9.40.8 well_known_port[3:2] priority- w ell k nown l ogic p ort 3 and 2 p riority i 2 c address h0ec, cpu address 596 accessed by cpu, serial interface and i 2 c (r/w) priority 2 - well known port 6000 for xwin. priority 3 - well known port 443 for http.sec (default 00) 14.9.40.9 well_known_port [5:4] priority- w ell k nown l ogic p ort 5 and 4 p riority i 2 c address h0ed, cpu address 597 accessed by cpu, serial interface and i 2 c (r/w) priority 4 - well known port 111 for sun remote procedure call. priority 5 - well known port 22555 for ip phone call setup. (default 00) 14.9.40.10 well_known_port [7:6] priority- w ell k nown l ogic p ort 7 and 6 p riority i 2 c address h0ee, cpu address 598 accessed by cpu, serial interface and i 2 c (r/w) priority 6 - well know port 22 for ssh. priority 7 ? well known port 554 for rtsp. (default 00) 754310 priority 3 drop priority 2 drop 754310 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop zl50418 data sheet 100 zarlink semiconductor inc. 14.9.40.11 well known_port_enable [7:0] ? w ell k nown l ogic 7 to 0 p ort e nables i 2 c address h0ef, cpu address 599 accessed by cpu, serial interface and i 2 c (r/w) - 1? enable -0 - disable (default 00) 14.9.40.12 rlowl ? u ser d efine r ange l ow b it 7:0 i 2 c address h0f4, cpu address: 59a accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.13 rlowh ? u ser d efine r ange l ow b it 15:8 i 2 c address h0f5, cpu address: 59b accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.14 rhighl ? u ser d efine r ange h igh b it 7:0 i 2 c address h0d3, cpu address: 59c accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.15 rhighh ? u ser d efine r ange h igh b it 15:8 i 2 c address h0d4, cpu address: 59d accessed by cpu, serial interface and i 2 c (r/w) (default 00) 14.9.40.16 rpriority ? u ser d efine r ange p riority i 2 c address h0d5, cpu address: 59e accessed by cpu, serial interface and i 2 c (r/w) 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 74310 range transmit priority drop zl50418 data sheet 101 zarlink semiconductor inc. rlow and rhigh form a range for l ogical ports to be classified with priority specified in rpriority. 14.9.41 cpuqosc123 cpu address: 5a0, 5a1, 5a2 accessed by cpu and serial interface (r/w) c - cpuqosc1 ? cpu byte_c1 i 2 c address h0c1, cpu address 517) b - cpuqosc2 ? cpu byte_c2 i 2 c address h0c2, cpu address 518) a - cpuqosc3 ? cpu byte_c3 i 2 c address h0c3, cpu address 519) represents values a-c for a cpu port. the values a-c are per-queue byte thresholds for random early drop. qosc3 represents a, and qosc1 represents c. granularity: 256 bytes 14.10 (group 6 address) misc group 14.10.1 mii_op0 ? mii register option 0 i 2 c address f0, cpu address:h600 accessed by cpu, serial interface and i 2 c (r/w) bit [3:1] transmit priority bits [0]: drop priority 76 5 4 0 hfc 1prst disj vendor spc. reg addr bits [7]: half duplex flow control feature 0 = half duplex flow control always enable 1 = half duplex flow control by negotiation bits [6]: link partner reset auto-negotiate disable bits [5]: disable jabber detection. this is for homepna applications or any serial operation slower than 10 mbps. 0 = enable 1 = disable bit [4:0]: vendor specified link status regist er address (null value means don?t use it) (default 00). this is used if the linkup bit position in the phy is non-standard zl50418 data sheet 102 zarlink semiconductor inc. 14.10.2 mii_op1 ? mii register option 1 i 2 c address f1, cpu address:h601 accessed by cpu, serial interface and i 2 c (r/w) 14.10.3 fen ? feature register i 2 c address f2, cpu address:h602) accessed by cpu, serial interface and i 2 c (r/w) 743 0 speed bit location duplex bit location bits [3:0]: duplex bit location in vendor specified register bits [7:4]: speed bit location in vendor specified register (default 00) 7 654 3 21 0 dml mii rp ip mul v-sp ds rc sc bits [0]: statistic counter enable (default 0) 0 ? disable 1 ? enable (all ports) when statistic counter is enable, an interr upt control frame is generated to the cpu, every time a counter wraps around. this feature requires an external cpu. bits [1]: rate control enable (default 0) ?0 ? disable ? 1 ? enable; must also set ecr2pn[3] = 1 this bit enables/disables the rate control for all 10/100 ports. to start rate control in a 10/100 port the rate control memory must be programmed. this feature requires an external cpu. see programming qos registers application note and processor interface application note for more information. bit [2]: support ds ef code. (default 0) ?0 ? disable ? 1 ? enable (all ports) when 101110 is detected in ds field (tos[7:2]), the frame priority is set for 110 and drop is set for 0. bit [3]: enable vlan spanning tree support (default 0) ?0 ? disable ? 1 ? enable when vlan spanning tree is enable the registers ecr1pn are not used to program the port spanning tree status. the port status is programmed using the control command frame. zl50418 data sheet 103 zarlink semiconductor inc. 14.10.4 miic0 ? mii command register 0 cpu address:h603 accessed by cpu and serial interface only (r/w) ? bit [7:0] - mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 14.10.5 miic1 ? mii command register 1 cpu address:h604 accessed by cpu and serial interface only (r/w) ? bit [7:0] - mii data [15:8] note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then pro- gram mii command. 14.10.6 miic2 ? mii command register 2 cpu address:h605 accessed by cpu and serial interface only (r/w) note: before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. bit [4]: disable ip multicast suppor t (default 1) ? 0 ? enable ip multicast support ? 1 ? disable ip multicast support when enable, igmp packets are identified by search engine and are passed to the cpu for processing. ip multicast packets are forwarded to the ip multicast group members according to the vlan port mapping table. bit [5]: enable report to cpu (default 0) ? 0 ? disable report to cpu ? 1 ? enable report to cpu when disable new vlan port associatio n report, new mac address report or aging reports are disable for all ports. when enable, register se_opemode is used to enable/disable selectively each function. bit [6]: disable mii management state machine (default 0) ? 0: enable mii management state machine ? 1: disable mii management state machine 7654 0 mii op register address ? bit [4:0] - reg_ad ? register phy address ? bit [6:5] - op ? operation code ?10? for read command and ?01? for write command zl50418 data sheet 104 zarlink semiconductor inc. 14.10.7 miic3 ? mii command register 3 cpu address:h606 accessed by cpu and serial interface only (r/w) note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. writing this r egister will initiate a serial manag ement cycle to the mii management interface. 14.10.8 miid0 ? mii data register 0 cpu address:h607 accessed by cpu and serial interface only (ro) ? bit [7:0] - mii data [7:0] 14.10.9 miid1 ? mii data register 1 cpu address:h608 accessed by cpu and serial interface only (ro) ? bit [7:0] - mii data [15:8] 14.10.10 led mode ? led control cpu address:h609 accessed by cpu, serial interface and i 2 c (r/w) 7654 0 rdy valid phy address ? bits [4:0] - phy_ad ? 5 bit phy address ? bit [6] - valid ? data valid from phy (read only) ? bit [7] - rdy ? data is returned from phy (ready only) 7543210 clock rate hold time ? bit [0] reserved(default 0) ? bit [2:1]: hold time for led signal (default 00) ? 00 = 8 msec 01 = 16 msec ? 10 = 32 msec 11=64 msec ? bit [4:3]: led clock frequency (default 0) ? 00 =100 m/8 = 12.5 mhz 01 = 100 m/16 = 25 mhz ? 10 = 100 m/32 = 125 mhz 11 = 100 m/64 = 1.5625 mhz ? bit [7:5]: reserved. must be set to ?0? (default 0) zl50418 data sheet 105 zarlink semiconductor inc. 14.10.11 device mode cpu address:h60a accessed by cpu and serial interface (r/w) bit [1:0]:reserved. must be set to ?0? (default 0) bit [2]: support <= 1536 frames 0: <= 1518 bytes (<= 1522 bytes with vlan tag) (default) 1: <= 1536 bytes bit [7:3]:reserved. must be set to ?0? (default 0) 14.10.12 checks um - eeprom checksum i 2 c address ff, cpu address:h60b accessed by cpu, serial interface and i 2 c (r/w) this register is used in unmanaged mode only. before requesting that the zl50 418 updates the eeprom device, the correct checksum needs to be calculated and written into this checksum regist er. the checksum formula is when the zl50418 boots from the eeprom the checksum is calculated and the value must be zero. if the checksum is not zeroed the zl50418 does not start and pin checksum_ok is set to zero. 14.11 (group 7 address) port mirroring group 14.11.1 mirror1_src ? port mirror source port cpu address 700 accessed by cpu and serial interface (r/w) (default 7f) ? bit [7:0]: (default 0) ff i 2 c register = 0 i = 0 7654 0 i/o src port select ? bit [4:0]: source port to be mirrored. us e illegal port number to disable mirroring ? bit [5]: 1 ? select ingress data 0 ? select egress data ? bit [6]: reserved ? bit [7]: reserved must be set to '1' zl50418 data sheet 106 zarlink semiconductor inc. 14.11.2 mirror1_dest ? port mirror destination cpu address 701 accessed by cpu, serial interface (r/w) (default 17) 14.11.3 mirror2_src ? port mirror source port cpu address 702 accessed by cpu, serial in terface (r/w) (default ff) 14.11.4 mirror2_dest ? port mirror destination cpu address 703 accessed by cpu, serial interface (r/w) (default 00) 754 0 dest port select ? bit [4:0]: port mirror destination when port mirroring is enable, destination port can not serve as a data port. 7654 0 i/o src port select ? bit [4:0]: source port to be mirrored. us e illegal port number to disable mirroring ? bit [5]: 1 ? select ingress data 0 ? select egress data ? bit [6] reserved ? bit [7] reserved must be set to '1' 754 0 dest port select ? bit [4:0]: port mirror destination when port mirroring is enable, destination port can not serve as a data port. zl50418 data sheet 107 zarlink semiconductor inc. 14.12 group f address) cpu access group 14.12.1 gcr-global control register cpu address: hf00 accessed by cpu and serial interface. (r/w) 14.12.2 dcr-device status and signature register cpu address: hf01 accessed by cpu and serial interface. (ro) 7543210 init reset bist sr sc bit [0]: store configuration (default = 0) write ?1? followed by ?0? to store configuration into external eeprom bit [1]: store configuration and reset (default = 0) write ?1? to store configuration into external eeprom and reset chip bit [2]: start bist (default = 0) write ?1? followed by ?0? to start the device?s built-in self-test. the result is found in the dcr register. bit [3]: soft reset (default = 0) write ?1? to reset chip bit [4]: initialization done (default = 0). this bit is meaningless in unmanaged mode. in managed mode, cpu write this bit with ?1? to indicate initializ ation is completed and ready to forward packets. 1 = initialization is done. 0 = initialization is not complete. 76543 2 10 revision signature re binp br bw bit [0]: 1: busy writin g configuration to i 2 c 0: not busy (not writing configuration to i 2 c) bit [1]: 1: busy reading configuration from i 2 c 0: not busy (not reading configuration from i 2 c) bit [2]: 1: bist in progress 0: bist not running bit [3]: 1: ram error 0: ram ok bit [5:4]: device signature 11: zl50418 device zl50418 data sheet 108 zarlink semiconductor inc. 14.12.2.1 dcr1-giga port status cpu address: hf02 accessed by cpu and serial interface. (ro) bit [7:6]: revision 00: initial silicon 01: xa1 silicon 10: production silicon 76 43210 cic giga1 giga0 bit [1:0]: giga port 0 strap option ? 00 ? 100 mb mii mode ? 01 ? reserved ? 10 ? gmii ? 11 ? pcs giga port 1 strap option bit[3:2] ? 00 ? 100 mb mii mode ? 01 ? reserved ? 10 ? gmii ? 11 ? pcs bit [7] chip initialization completed zl50418 data sheet 109 zarlink semiconductor inc. 14.12.3 dpst ? device port status register cpu address:hf03 accessed by cpu and serial interface (r/w) 14.12.4 dtst ? data read back register cpu address: hf04 accessed by cpu and serial interface (ro) this register provides various internal information as selected in dpst bit [4:0]. refer to the phy control application note. bit[4:0]: read back index register. this is used for selecting what to read back from dtst. (default 00) - 5?b00000 - port 0 operating mode and negotiation status - 5?b00001 - port 1 operating mode and negotiation status - 5?b00010 - port 2 operating mode and negotiation status - 5?b00011 - port 3 operating mode and negotiation status - 5?b00100 - port 4 operating mode and negotiation status - 5?b00101 - port 5 operating mode and negotiation status - 5?b00110 - port 6 operating mode and negotiation status - 5?b00111 - port 7 operating mode and negotiation status - 5?b01000 - port 8 operating mode and negotiation status - 5?b01001 - port 9 operating mode and negotiation status - 5?b01010 - port 10 operating mode and negotiation status - 5?b01011 - port 11 operating mode and negotiation status - 5?b01100 - port 12 operating mode and negotiation status - 5?b01101 - port 13 operating mode and negotiation status - 5?b01110 - port 14 operating mode and negotiation status - 5?b01111 - port 15 operating mode and negotiation status - 5?b10000 - reserved - 5?b10001 - reserved - 5?b10010 - reserved - 5?b00011 - reserved - 5?b10100 - reserved - 5?b10101 - reserved - 5?b10110 - reserved - 5?b10111 - reserved - 5?b11000 - port 24 operating mode/neg status (cpu port) - 5?b11001 - port 25 operating mode/neg status (gigabit 1) - 5?b11010 - port 26 operating mode/neg status (gigabit 2) 76543210 md info sig giga inkdn fe fdpx fcen zl50418 data sheet 110 zarlink semiconductor inc. when bit is 1: bit [0] ? flow control enable bit [1] ? full duplex port bit [2] ? fast ethernet port (if not gigabit port) bit [3] ? link is down bit [4] ? giga port bit [5] ? signal detect (when pcs interface mode) bit [6] - reserved bit [7] ? module detected (for hot swap purpose) 14.12.5 pllcr - pll control register cpu address: hf05 accessed by serial interface (rw) bit [3] - must be '1' bit [7] - selects strap option or lclk/oeclk registers 0 - strap option (default) 1 - lclk/oeclk registers 14.12.6 lclk - la_clk delay from internal oe_clk cpu address: hf06 accessed by serial interface (rw) pd[12:10] lclk delay 000b 80h 8 buffers delay 001b 40h 7 buffers delay 010b 20h 6 buffers delay 011b 10h 5 buffers delay (recommend) 100b 08h 4 buffers delay 101b 04h 3 buffers delay 110b 02h 2 buffers delay 111b 01h 1 buffers delay the lclk delay from sclk is the sum of the delay programmed in here and the delay in oeclk register. zl50418 data sheet 111 zarlink semiconductor inc. 14.12.7 oeclk - internal oe_clk delay from sclk cpu address: hf07 accessed by serial interface (rw) the oe_clk is used for generating the oe0 and oe1 signals. pd[15:13] oeclk delay 000b 80h 8 buffers delay 001b 40h 7 buffers delay (recommend) 010b 20h 6 buffers delay 011b 10h 5 buffers delay 100b 08h 4 buffers delay 101b 04h 3 buffers delay 110b 02h 2 buffers delay 111b 01h 1 buffers delay 14.12.8 da ? da register cpu address: hfff accessed by cpu and serial interface (ro) always return 8?h da . indicate the cpu interface or serial port connection is good. 14.13 tbi registers two sets of tbi registers are used for configure the two gigabit ports if they are operating in tbi mode. these tbi registers are located inside the switching chip and th ey are accessed through the mii command and mii data registers. 14.13.1 control register mii address: h00 read/write bit [15] reset pcs logic and all tbi registers 1 = reset. 0 = normal operation. bit [14] reserved. must be programmed with ?0?. bit [13] speed selection (see bit 6 for complete details) bit [12] auto negotiation enable 1 = enable auto-negotiation process. 0 = disable auto-negotiation process (default). bit [11:10] reserved. must be programmed with ?0? zl50418 data sheet 112 zarlink semiconductor inc. 14.13.2 status register mii address: h01 read only bit [9] restart auto negotiation. 1 = restart auto-negotiation process. 0 = normal operation (default). bit [8:7] reserved. bit [6] speed selection bit [6][13] 11= reserved 0 0 = 1000 mb/s (default) 0 1 =100 mb/s 00=10mb/s bit [5:0] reserved. must be programmed with ?0?. bit [15:9] reserved. always read back as ?0?. bit [8] reserved. always read back as ?1?. bit [7:6] reserved. always read back as ?0?. bit [5] auto-negotiation complete 1 = auto-negotiation process completed. 0 = auto-negotiation process not completed. bit [4] reserved. always read back as ?0? bit [3] reserved. always read back as ?1? bit [2] link status 1 = link is up. 0 = link is down. bit [1] reserved. always read back as ?0?. bit [0] reserved. always read back as ?1?. zl50418 data sheet 113 zarlink semiconductor inc. 14.13.3 advertisement register mii address: h04 read/write 14.13.4 link partner ability register mii address: h05 read only bit [15] next page 1 = has next page capabilities. 0 = do not has next page capabilities (default). bit [14] reserved. always read back as ?0?. read only. bit [13:12] remote fault. default is ?0?. bit [11:9] reserved. always read back as ?0?. read only. bit [8:7] pause. default is ?00? bit [6] half duplex 1 = support half duplex (default). 0 = do not support half duplex. bit [5] full duplex 1 = support full duplex (default). 0 = do not support full duplex. bit [4:0] reserved. always read back as ?0?. read only. bit [15] next page 1 = has next page capabilities. 0 = do not has next page capabilities. bit [14] acknowledge bit [13:12] remote fault. bit [11:9] reserved. always read back as ?0?. bit [8:7] pause. bit [6] half duplex 1 = support half duplex. 0 = do not support half duplex. bit [5] full duplex 1 = support full duplex. 0 = do not support full duplex. bit [4:0] reserved. always read back as ?0?. zl50418 data sheet 114 zarlink semiconductor inc. 14.13.5 expansion register mii address: h06 read only 14.13.6 extended status register mii address: h15 read only bit [15:2] reserved. always read back as ?0?. bit [1] page received. 1 = a new page has been received. 0 = a new page has not been received. bit [0] reserved. always read back as ?0?. bit [15] 1000 full duplex 1 = support 1000 full duplex operation (default). 0 = do not support 1000 full duplex operation. bit [14] 1000 half duplex 1 = support 1000 half duplex operation (default). 0 = do not support 1000 half duplex operation. bit [13:0] reserved. always read back as ?0?. zl50418 data sheet 115 zarlink semiconductor inc. 15.0 bga and ba ll signal descriptions 15.1 bga views (top views) 15.1.1 encapsulated view in unmanaged mode 1 234567891011121314151617181920212223242526272829 ala_d 4 la_d 7 la_d 10 la_d 13 la_d 15 la_a 4 la_o e0_ la_a 8 la_a 13 la_a 16 la_a 19 la_d 33 la_d 36 la_d 39 la_d 42 la_d 45 oe_ clk0 la_ clk0 trun k1 rese rved rese rved scl sda stro be tsto ut7 bla_d 1 la_d 3 la_d 6 la_d 9 la_d 12 la_d 14 la_a dsc_ la_o e1_ la_a 7 la_a 12 la_a 15 la_a 18 la_d 32 la_d 35 la_d 38 la_d 41 la_d 44 oe_ clk1 la_ clk1 la_d 62 rese rved rese rved trun k2 rese rved d0 tsto ut8 tsto ut3 cla_c lk la_d 0 la_d 2 la_d 5 la_d 8 la_d 11 la_a 3 la_o e_ la_w e_ t_mo de1 la_a 11 la_a 14 la_a 17 la_a 20 la_d 34 la_d 37 la_d 40 la_d 43 oe_ clk2 la_ clk2 p_d trun k0 rese rved rese rved auto fd tsto ut11 tsto ut9 tsto ut4 tsto ut0 d agn d la_d 17 la_d 19 la_d 21 la_d 23 la_d 25 la_d 27 la_d 29 la_d 31 la_a 6 la_a 10 la_w e0_ la_d 49 la_d 51 la_d 53 la_d 55 la_d 57 la_d 59 la_d 61 la_d 63 la_d 47 scan col scan clk tsto ut14 tsto ut13 tsto ut12 tsto ut10 tsto ut5 tsto ut1 esclk la_d 16 la_d 18 la_d 20 la_d 22 la_d 24 la_d 26 la_d 28 la_d 30 la_a 5 la_a 9 la_w e1_ la_d 48 la_d 50 la_d 52 la_d 54 la_d 56 la_d 58 la_d 60 rese rved la_d 46 scan link tsto ut15 m26_ crs m26_ txer scan mod tsto ut6 tsto ut2 f av c c resi n_ scan en lb_d 63 lb_d 62 vcc vcc vcc vcc vcc m26_ txcl m26_ txen m26_ mtx- m26_ rxdv m26_ rxcl g lb_c lk rese tout lb_d 47 lb_d 61 lb_d 60 rese rved rese rved rese rved m26_ rxer m26_ col hlb_d 46 lb_d 45 lb_d 44 lb_d 59 lb_d 58 rese rved rese rved rese rved rese rved rese rved jlb_d 43 lb_d 42 lb_d 41 lb_d 57 lb_d 56 rese rved rese rved m26_ rxd9 rese rved rese rved klb_d 40 lb_d 39 lb_d 38 lb_d 55 lb_d 54 vdd vdd vdd vdd m26_ txd9 m26_ txd8 m26_ rxd6 m26_ rxd7 m26_ rxd8 llb_d 37 lb_d 36 lb_d 35 lb_d 53 lb_d 52 m26_ txd4 m26_ txd6 m26_ rxd3 m26_ rxd4 m26_ rxd5 mlb_d 34 lb_d 33 lb_d 32 lb_d 51 lb_d 50 vdd vss vss vss vss vss vss vss vdd m26_ txd7 m26_ txd5 m26_ rxd0 m26_ rxd1 m26_ rxd2 nlb_a 18 lb_a 19 lb_a 20 lb_d 49 lb_d 48 vcc vdd vss vss vss vss vss vss vss vdd vcc m26_ txd2 m26_ txd3 gref _clk plb_a 15 lb_a 16 lb_a 17 lb_w e0_ lb_w e1_ vcc vss vss vss vss vss vss vss vcc m26_ txd0 m26_ txd1 mdio gref _clk rlb_a 10 lb_a 11 lb_a 12 lb_a 13 lb_a 14 vcc vss vss vss vss vss vss vss vcc m25_ crs m25_ txer mdc m_cl k tlb_a 5 lb_a 6 lb_a 7 lb_a 8 lb_a 9 vcc vss vss vss vss vss vss vss vcc m25_ txcl m25_ txen m25_ mtx- m25_ rxdv m25_ rxcl ulb_o e0_ lb_o e1_ t_mo de0 lb_d 31 lb_d 30 vcc vdd vss vss vss vss vss vss vss vdd vcc rese rved rese rved rese rved m25_ rxer m25_ col vlb_a dsc_ lb_o e_ lb_w e_ lb_d 29 lb_d 28 vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved wlb_d 15 lb_a 3 lb_a 4 lb_d 27 lb_d 26 rese rved rese rved m25_ rxd9 rese rved rese rved ylb_d 14 lb_d 13 lb_d 12 lb_d 25 lb_d 24 vdd vdd vdd vdd m25_ rxd6 m25_ txd9 m25_ txd8 m25_ rxd7 m25_ rxd8 aa lb_d 11 lb_d 10 lb_d 9 lb_d 23 lb_d 22 m25_ txd6 m25_ txd7 m25_ rxd3 m25_ rxd4 m25_ rxd5 ab lb_d 8 lb_d 7 lb_d 6 lb_d 21 lb_d 20 m25_ txd4 m25_ txd5 m25_ rxd0 m25_ rxd1 m25_ rxd2 ac lb_d 5 lb_d 4 lb_d 3 lb_d 19 lb_d 18 m25_ txd2 m25_ txd3 rese rved rese rved rese rved ad lb_d 2 lb_d 1 lb_d 0 lb_d 17 lb_d 16 vcc vcc vcc vcc vcc m25_ txd0 m25_ txd1 rese rved rese rved rese rved ae m0_t xen m0_t xd0 m0_t xd1 m3_t xd1 m3_t xen m3_r xd0 m5_t xd1 m5_t xen m5_r xd0 m8_t xd1 m8_t xen m8_r xd0 m10_ txd1 m10_ txen m10_ rxd0 m13_ txd1 rese rved m15_ txd1 rese rved m15_ txen m15_ rxd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved af m0_r xd1 m0_r xd0 m0_c rs m3_t xd0 m3_c rs m3_r xd1 m5_t xd0 m5_c rs m5_r xd1 m8_t xd0 m8_c rs m8_r xd1 m10_ txd0 m10_ crs m10_ rxd1 m13_ txd0 m13_ crs m13_ rxd1 m14_ crs rese rved m15_ rxd1 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved ag m1_t xen m1_t xd0 m1_t xd1 m2_t xd1 m2_c rs m4_t xd1 m4_c rs m6_t xd1 m6_c rs m7_t xd1 m7_c rs m9_t xd1 m9_c rs m11_ txd1 m11_ crs m12_ txd1 m12_ crs m14_ txd1 m15_ txd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved ah m1_r xd0 m1_c rs m2_t xd0 m2_r xd0 m4_t xd0 m4_r xd0 m6_t xd0 m6_r xd0 m7_t xd0 m7_r xd0 m9_t xd0 m9_r xd0 m11_ txd0 m11_ rxd0 m12_ txd0 m12_ rxd0 m14_ txd0 m14_ rxd0 m13_ rxd0 m15_ crs rese rved rese rved rese rved rese rved rese rved rese rved rese rved aj m1_r xd1 m2_t xen m2_r xd1 m4_t xen m4_r xd1 m6_t xen m6_r xd1 m7_t xen m7_r xd1 m9_t xen m9_r xd1 m11_ txen m11_ rxd1 m12_ txen m12_ rxd1 m14_ txen m14_ rxd1 rese rved m13_ txen rese rved rese rved rese rved rese rved rese rved rese rved 1234567891011121314151617181920212223242526272829 zl50418 data sheet 116 zarlink semiconductor inc. 15.1.2 encapsulated view in managed mode 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526272829 a la_d 4 la_d 7 la_d 10 la_d 13 la_d 15 la_a 4 la_o e0_ la_a 8 la_a 13 la_a 16 la_a 19 la_d 33 la_d 36 la_d 39 la_d 42 la_d 45 p_da ta13 p_da ta10 p_da ta7 p_da ta4 p_da ta1 p_a0 p_a1 p_we tsto ut7 b la_d 1 la_d 3 la_d 6 la_d 9 la_d 12 la_d 14 la_a dsc_ la_o e1_ la_a 7 la_a 12 la_a 15 la_a 18 la_d 32 la_d 35 la_d 38 la_d 41 la_d 44 p_da ta14 p_da ta11 la_d 62 p_da ta5 p_da ta2 p_da ta6 p_intp_rd tsto ut8 tsto ut3 c la_c lk la_d 0 la_d 2 la_d 5 la_d 8 la_d 11 la_a 3 la_o e_ la_w e_ t_mo de1 la_a 11 la_a 14 la_a 17 la_a 20 la_d 34 la_d 37 la_d 40 la_d 43 p_da ta15 p_da ta12 p_da ta9 p_a2 p_da ta3 p_da ta0 p_cs tsto ut11 tsto ut9 tsto ut4 tsto ut0 d agnd la_d 17 la_d 19 la_d 21 la_d 23 la_d 25 la_d 27 la_d 29 la_d 31 la_a 6 la_a 10 la_w e0_ la_d 49 la_d 51 la_d 53 la_d 55 la_d 57 la_d 59 la_d 61 la_d 63 la_d 47 scan col scan clk tsto ut14 tsto ut13 tsto ut12 tsto ut10 tsto ut5 tsto ut1 e sclk la_d 16 la_d 18 la_d 20 la_d 22 la_d 24 la_d 26 la_d 28 la_d 30 la_a 5 la_a 9 la_w e1_ la_d 48 la_d 50 la_d 52 la_d 54 la_d 56 la_d 58 la_d 60 p_da ta8 la_d 46 scan link tsto ut15 m26_ crs m26_ txer scan mod e tsto ut6 tsto ut2 f avcc resi n_ scan en lb_d 63 lb_d 62 vcc vcc vcc vcc vcc m26_ txcl k m26_ txen m26_ mtxc lk m26_ rxdv m26_ rxcl k g lb_c lk rese tout _ lb_d 47 lb_d 61 lb_d 60 rese rved rese rved rese rved m26_ rxer m26_ col h lb_d 46 lb_d 45 lb_d 44 lb_d 59 lb_d 58 rese rved rese rved rese rved rese rved rese rved j lb_d 43 lb_d 42 lb_d 41 lb_d 57 lb_d 56 rese rved rese rved m26_ rxd9 rese rved rese rved k lb_d 40 lb_d 39 lb_d 38 lb_d 55 lb_d 54 vdd vdd vdd vdd m26_ txd9 m26_ txd8 m26_ rxd6 m26_ rxd7 m26_ rxd8 l lb_d 37 lb_d 36 lb_d 35 lb_d 53 lb_d 52 m26_ txd4 m26_ txd6 m26_ rxd3 m26_ rxd4 m26_ rxd5 m lb_d 34 lb_d 33 lb_d 32 lb_d 51 lb_d 50 vdd vss vss vss vss vss vss vss vdd m26_ txd7 m26_ txd5 m26_ rxd0 m26_ rxd1 m26_ rxd2 n lb_a 18 lb_a 19 lb_a 20 lb_d 49 lb_d 48 vcc vdd vss vss vss vss vss vss vss vdd vcc m26_ txd2 m26_ txd3 gref _clk 1 p lb_a 15 lb_a 16 lb_a 17 lb_w e0_ lb_w e1_ vcc vss vss vss vss vss vss vss vcc m26_ txd0 m26_ txd1 mdio gref _clk 0 r lb_a 10 lb_a 11 lb_a 12 lb_a 13 lb_a 14 vcc vss vss vss vss vss vss vss vcc m25_ crs m25_ txer mdc m_cl k t lb_a 5 lb_a 6 lb_a 7 lb_a 8 lb_a 9 vcc vss vss vss vss vss vss vss vcc m25_ txcl k m25_ txen m25_ mtxc lk m25_ rxdv m25_ rxcl k u lb_o e0_ lb_o e1_ t_mo de0 lb_d 31 lb_d 30 vcc vdd vss vss vss vss vss vss vss vdd vcc rese rved rese rved rese rved m25_ rxer m25_ col v lb_a dsc_ lb_o e_ lb_w e_ lb_d 29 lb_d 28 vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved w lb_d 15 lb_a 3 lb_a 4 lb_d 27 lb_d 26 rese rved rese rved m25_ rxd9 rese rved rese rved y lb_d 14 lb_d 13 lb_d 12 lb_d 25 lb_d 24 vdd vdd vdd vdd m25_ rxd6 m25_ txd9 m25_ txd8 m25_ rxd7 m25_ rxd8 aa lb_d 11 lb_d 10 lb_d 9 lb_d 23 lb_d 22 m25_ txd6 m25_ txd7 m25_ rxd3 m25_ rxd4 m25_ rxd5 ab lb_d 8 lb_d 7 lb_d 6 lb_d 21 lb_d 20 m25_ txd4 m25_ txd5 m25_ rxd0 m25_ rxd1 m25_ rxd2 ac lb_d 5 lb_d 4 lb_d 3 lb_d 19 lb_d 18 m25_ txd2 m25_ txd3 rese rved rese rved rese rved ad lb_d 2 lb_d 1 lb_d 0 lb_d 17 lb_d 16 vcc vcc vcc vcc vcc m25_ txd0 m25_ txd1 rese rved rese rved rese rved ae m0_t xen m0_t xd0 m0_t xd1 m3_t xd1 m3_t xen m3_r xd0 m5_t xd1 m5_t xen m5_r xd0 m8_t xd1 m8_t xen m8_r xd0 m10_ txd1 m10_ txen m10_ rxd0 m13_ txd1 rese rved m15_ txd1 rese rved m15_ txen m15_ rxd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved af m0_r xd1 m0_r xd0 m0_c rs m3_t xd0 m3_c rs m3_r xd1 m5_t xd0 m5_c rs m5_r xd1 m8_t xd0 m8_c rs m8_r xd1 m10_ txd0 m10_ crs m10_ rxd1 m13_ txd0 m13_ crs m13_ rxd1 m14_ crs rese rved m15_ rxd1 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved ag m1_t xen m1_t xd0 m1_t xd1 m2_t xd1 m2_c rs m4_t xd1 m4_c rs m6_t xd1 m6_c rs m7_t xd1 m7_c rs m9_t xd1 m9_c rs m11_ txd1 m11_ crs m12_ txd1 m12_ crs m14_ txd1 m15_ txd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved ah m1_r xd0 m1_c rs m2_t xd0 m2_r xd0 m4_t xd0 m4_r xd0 m6_t xd0 m6_r xd0 m7_t xd0 m7_r xd0 m9_t xd0 m9_r xd0 m11_ txd0 m11_ rxd0 m12_ txd0 m12_ rxd0 m14_ txd0 m14_ rxd0 m13_ rxd0 m15_ crs rese rved rese rved rese rved rese rved rese rved rese rved rese rved aj m1_r xd1 m2_t xen m2_r xd1 m4_t xen m4_r xd1 m6_t xen m6_r xd1 m7_t xen m7_r xd1 m9_t xen m9_r xd1 m11_ txen m11_ rxd1 m12_ txen m12_ rxd1 m14_ txen m14_ rxd1 rese rved m13_ txen rese rved rese rved rese rved rese rved rese rved rese rved 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 zl50418 data sheet 117 zarlink semiconductor inc. 15.2 ball ? signal descriptions in managed mode all pins are cmos type; all input pins are 5 volt tolerance; and all output pins are 3.3 cmos drive. 15.2.1 ball signal descriptions in managed mode ball no(s) symbol i/o description cpu bus interface in managed mode c19, b19, a19, c20, b20, a20, c21, e20, a21, b24, b22, a22, c23, b23, a23, c24 p_data[15:0] i/o-ts with pull up except p_data[7:6] i/o-ts with pull down processor bus data bit [15:0]. p_data[7:0] is used in 8-bit mode. c22, a24, a25 p_a[2:0] input processor bus address bit [2:0] a26 p_we# input with weak internal pull up cpu bus-write enable b26 p_rd# input with weak internal pull up cpu bus-read enable c25 p_cs# input with weak internal pull up chip select b25 p_int# output cpu interrupt frame buffer interface d20, b21, d19, e19,d18, e18, d17, e17, d16, e16, d15, e15, d14, e14, d13, e13, d21, e21, a18, b18, c18, a17, b17, c17, a16, b16, c16, a15, b15, c15, a14, b14, d9, e9, d8, e8, d7, e7, d6, e6, d5, e5, d4, e4, d3, e3, d2, e2, a7, b7, a6, b6, c6, a5, b5, c5, a4, b4, c4, a3, b3, c3, b2, c2 la_d[63:0] i/o-ts with pullup f rame bank a? data bit [63:0] c14, a13, b13, c13, a12, b12, c12, a11, b11, c11, d11, e11, a10, b10, d10, e10, a8, c7 la_a[20:3] output frame bank a ? address bit [20:3] b8 la_adsc# output with pull up frame bank a address status control c1 la_clk output frame bank a clock input c9 la_we# output with pull up frame bank a write chip select for one layer sram configuration d12 la_we0# output with pull up frame bank a write chip select for lower layer of two layers sram configuration zl50418 data sheet 118 zarlink semiconductor inc. e12 la_we1# output with pull up frame bank a write chip select for upper layer of two layers sram configuration c8 la_oe# output with pull up frame bank a read chip select for one bank sram configuration a9 la_oe0# output with pull up frame bank a read chip select for lower layer of two layers sram configuration b9 la_oe1# output with pull up frame bank a read chip select for upper layer of two layers sram configuration f4, f5, g4, g5, h4, h5, j4, j5, k4, k5, l4, l5, m4, m5, n4, n5, g3, h1, h2, h3, j1, j2, j3, k1, k2, k3, l1, l2, l3, m1, m2, m3, u4, u5, v4, v5, w4, w5, y4, y5, aa4, aa5, ab4, ab5, ac4, ac5, ad4, ad5, w1, y1, y2, y3, aa1, aa2, aa3, ab1, ab2, ab3, ac1, ac2, ac3, ad1, ad2, ad3 lb_d[63:0] i/o-ts with pullup. frame bank b? data bit [63:0] n3, n2, n1, p3, p2, p1, r5, r4, r3, r2, r1, t5, t4, t3, t2, t1, w3, w2 lb_a[20:3] output frame bank b ? address bit [20:3] v1 lb_adsc# output with pull up frame bank b address status control g1 lb_clk output with pull up frame bank b clock input v3 lb_we# output with pull up frame bank b write chip select for one layer sram configuration p4 lb_we0# output with pull up frame bank b write chip select for lower layer of two layer sram configuration p5 lb_we1# output with pull up frame bank b write chip select for upper layer of two layers sram configuration v2 lb_oe# output with pull up frame bank b read chip select for one layer sram configuration u1 lb_oe0# output with pull up frame bank b read chip select for lower layer of two layers sram configuration u2 lb_oe1# output with pull up frame bank b read chip select for upper layer of two layers sram configuration ball no(s) symbol i/o description zl50418 data sheet 119 zarlink semiconductor inc. fast ethernet access ports [15:0] rmii r28 m_mdc output mii mana gement data clock ? (common for all mii ports [15:0]) p28 m_mdio i/o-ts with pull up mii management data i/o ? (common for all mii ports ?[15:0])) r29 m_clki input reference input clock af21, aj19, af18, aj17, aj15, af15, aj13, af12, aj11, aj9, af9, aj7, af6, aj5, aj3, af1 m[15:0]_rxd[1] input with weak internal pull up resistors. ports [15:0] ? receive data bit [1] ae21, ah19, ah20, ah17, ah15, ae15, ah13, ae12, ah11, ah9, ae9, ah7, ae6, ah5, ah2, af2 m[15:0]_rxd[0] input with weak internal pull up resistors ports [15:0] ? receive data bit [0] ah21, af19, af17, ag17, ag15, af14, ag13, af11, ag11, ag9, af8, ag7, af5, ag5, ah3, af3 m[15:0]_crs_ dv input with weak internal pull down resistors. ports [15:0] ? carrier sense and receive data valid aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1 m[15:0]_txen i/o- ts with pull up, slew ports [15:0] ? transmit enable strap option for rmii/gpsi ae18, ag18, ae16, ag16, ag14, ae13, ag12, ae10, ag10, ag8, ae7, ag6, ae4, ag4, ag3, ae3 m[15:0]_txd[1] output, slew ports [15:0] ? transmit data bit [1] ag19, ah18, af16, ah16, ah14, af13, ah12, af10, ah10, ah8, af7, ah6, af4, ah4, ag2, ae2 m[15:0]_txd[0] output, slew ports [15:0] ? transmit data bit [0] gmii/tbi gigabit ethern et access ports 0 & 1 y27, y26, aa26, aa25, ab26, ab25, ac26, ac25, ad26, ad25 m25_txd[9:0] output transmit data bit [9:0] t28 m25_rx_dv input w/ pull down receive data valid u28 m25_rx_er input w/ pull up receive error r25 m25_crs input w/ pull down carrier sense u29 m25_col input w/ pull up collision detected t29 m25_rxclk input w/ pull up receive clock ball no(s) symbol i/o description zl50418 data sheet 120 zarlink semiconductor inc. w27, y29, y28, y25, aa29, aa28, aa27, ab29, ab28, ab27 m25_rxd[9:0] input w/ pull up receive data bit [9:0] t26 m25_tx_en output w/ pull up transmit data enable r26 m25_tx_er output w/ pull up transmit error t27 m25_ mtxclk input w/ pull down mii mode transmit clock t25 m25_ txclk output gigabit transmit clock p29 gref_clk0 input w/ pull up gigabit reference clock k25, k26, m25, l26, m26, l25, n26, n25, p26, p25 m26_txd[9:0] output transmit data bit [9:0] f28 m26_rx_dv input w/ pull down receive data valid g28 m26_rx_er input w/ pull up receive error e25 m26_crs input w/ pull down carrier sense g29 m26_col input w/ pull up collision detected f29 m26_rxclk input w/ pull up receive clock j27, k29, k28, k27, l29, l28, l27, m29, m28, m27 m26_rxd[9:0] input w/ pull up receive data bit [9:0] f26 m26_tx_en output w/ pull up transmit data enable e26 m26_tx_er output w/ pull up transmit error f27 m26_ mtxclk input w/ pull down mii mode transmit clock f25 m26_ txclk output gigabit transmit clock n29 gref_clk1 input w/ pull up gigabit reference clock led interface c29 led_clk/tst out0 i/o- ts with pull up led serial interface output clock d29 led_syn/tst out1 i/o- ts with pull up led output data stream envelope e29 led_bit/tsto ut2 i/o- ts with pull up led serial data output stream b28 g1_rxtx#/ts tout3 i/o- ts with pull up led for gigabit port 1 (receive + transmit) c28 g1_dpcol#/t stout4 i/o- ts with pull up led for gigabit port 1 (full duplex + collision) d28 g1_link#/tst out5 i/o- ts with pull up led for gigabit port 1 ball no(s) symbol i/o description zl50418 data sheet 121 zarlink semiconductor inc. e28 g2_rxtx#/ts tout6 i/o- ts with pull up led for gigabit port 2 (receive + transmit) a27 g2_dpcol#/t stout7 i/o- ts with pull up led for gigabit port 2 (full duplex + collision) b27 g2_link#/tst out8 i/o- ts with pull up led for gigabit port 2 c27 init_done/ts tout9 i/o- ts with pull up system start operation d27 init_start/ts tout10 i/o- ts with pull up start initialization c26 checksum_o k/tstout11 i/o- ts with pull up eeprom read ok d26 fcb_err/tst out12 i/o- ts with pull up fcb memory self test fail d25 mct_err/tst out13 i/o- ts with pull up mct memory self test fail d24 bist_in_prc/ tstout14 i/o- ts with pull up processing memory self test e24 bist_done/ts tout15 i/o- ts with pull up memory self test done test facility u3, c10 t_mode0, t_mode1 i/o-ts test pins 00 ? test mode ? set mode upon reset, and provides nand tree test output during test mode 01 - reserved - do not use 10 - reserved - do not use 11 ? normal mode. use external pull up for normal mode ball no(s) symbol i/o description f3 scan_en input with pull down scan enable e27 scanmode input with pull down 1 ? enable test mode 0 - normal mode (open) ball no(s) symbol i/o description zl50418 data sheet 122 zarlink semiconductor inc. system clock, power, and ground pins e1 sclk input system clock at 100 mhz k12, k13, k17,k18 m10, n10, m20, n20, u10, v10, u20, v20, y12, y13, y17, y18 vdd power +2.5 volt dc supply f13, f14, f15, f16, f17, n6, p6, r6, t6, u6, n24, p24, r24, t24, u24, ad13, ad14, ad15, ad16, ad17 vcc power +3.3 volt dc supply m12, m13, m14, m15, m16, m17, m18, n12, n13, n14, n15, n16, n17, n18, p12, p13, p14, p15, p16, p17, p18, r12, r13, r14, r15, r16, r17, r18, t12, t13, t14, t15, t16, t17, t18, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v18, vss power ground ground f1 avcc analog power analog +2.5 volt dc supply d1 agnd analog ground analog ground misc d22 scancol input/ output scans the collision signal of home phy d23 scanclk output clock for scanning home phy collision and link e23 scanlink input/ output link up signal from home phy f2 resin# input reset input g2 resetout# output reset phy ball no(s) symbol i/o description zl50418 data sheet 123 zarlink semiconductor inc. ac29, ae28, aj27, af27, aj25, af24, ah23, ae19, ac27, af29, ag27, af26, ag25, ag23, af23, ag21, ac28, af28, ah27, ae27, ah25, ae24, af22, af20, ad29, ag28, aj26, ae26, aj24, ae23, aj22, aj20, ad27, ah28, ag26, ae25, ag24, ae22, aj23, ag20, ad28, ag29, ah26, af25, ah24, ag22, ah22, ae17, g27, h29, h28, h27, j29, j28, u26, u25, v26, v25, w26, w25, g26, g25, h26, h25, j26, j25, u27, v29, v28, v27, w29, w28 reserved na reserved pins. leave unconnected. bootstrap pins (default = pull up, 1= pull up 0= pull down) after reset tstout0 to tstou15 are used by the led interface. c29 tstout0 default 1 giga link polarity 0 ? active low 1 ? active high d29 tstout1 default 1 rmii mac power saving enable 0 ? no power saving 1 ? power saving e29 tstout2 default 1 recommend disable (0) with pull-down giga half duplex support 0 - disable 1 - enable b28 tstout3 default 1 module detect enable 0 ? hot swap enable 1 ? hot swap disable c28 tstout4 reserved d28 tstout5 default 1 scan speed: ? sclk or sclk 0 ? ? sclk (hpna) 1 - sclk e28 tstout6 default 1 cpu port mode 0 - 8 bit bus mode 1 - 16 bit bus mode ball no(s) symbol i/o description zl50418 data sheet 124 zarlink semiconductor inc. a27 tstout7 default 1 memory size 0 - 256 k x 32 or 256 k x 64 (4 m total) 1 - 128 k x 32 or 128 k x 64 (2 m total) b27 tstout8 default 1 eeprom installed 0 ? eeprom installed 1 ? eeprom not installed c27 tstout9 default 1 mct aging 0 ? mct aging disable 1 ? mct aging enable d27 tstout10 default 1 fcb aging 0 - fcb aging disable 1 ? fcb aging enable c26 tstout11 default 1 timeout reset 0 - timeout reset disable 1 - timeout reset enable. issue reset if any state machine did not go back to idle for 5 secs. d26 tstout12 reserved d25 tstout13 default 1 fdb ram depth (1 or 2 layers) 0 ? 2 layer 1 ? 1 layer d24 tstout14 default 1 cpu installed 0 ? cpu installed 1 ? cpu not installed e24 tstout15 default 1 sram test mode 0 ? enable test mode 1 ? normal operation t26, r26 g0_txen, g0_txer default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ball no(s) symbol i/o description zl50418 data sheet 125 zarlink semiconductor inc. notes: # =active low signal input =input signal in-st = input signal with schmitt-trigger output =output signal (tri-state driver) out-od=output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od =input & output signal with open-drain driver f26, e26 g1_txen, g1_txer default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1 m[15:0] txen default: rmii 0 ? gpsi 1 ? rmii c21 p_d[9] must be pulled-down reserved - must be pulled-down c19, b19, a19 p_d[15:13] default: 111 programmable delay for internal oe_clk from sclk input. the oe_clk is used for generating the oe0 and oe1 signals suggested value is 001. c20, b20, a20 p_d[12:10] default: 111 programmable delay for la_clk and lb_clk from internal oe_clk . the la_clk and lb_clk delay from sclk is the sum of the delay programmed in here and the delay in p_d[15:13]. suggested value is 011. ball no(s) symbol i/o description zl50418 data sheet 126 zarlink semiconductor inc. 15.2.2 ball ? signal descriptions in unmanaged mode ball no(s) symbol i/o description i 2 c interface note: in unmanaged mode, use i 2 c and serial control interface to configure the system a24 scl output i 2 c data clock a25 sda i/o-ts with internal pull up i 2 c data i/o serial control interface a26 strobe input with weak internal pull up serial strobe pin b26 d0 input with weak internal pull up serial data input c25 autofd output with pull up serial data output (autofd) frame buffer interface d20, b21, d19, e19,d18, e18, d17, e17, d16, e16, d15, e15, d14, e14, d13, e13, d21, e21, a18, b18, c18, a17, b17, c17, a16, b16, c16, a15, b15, c15, a14, b14, d9, e9, d8, e8, d7, e7, d6, e6, d5, e5, d4, e4, d3, e3, d2, e2, a7, b7, a6, b6, c6, a5, b5, c5, a4, b4, c4, a3, b3, c3, b2, c2 la_d[63:0] i/o-ts with pull up frame bank a? data bit [63:0] c14, a13, b13, c13, a12, b12, c12, a11, b11, c11, d11, e11, a10, b10, d10, e10, a8, c7 la_a[20:3] output frame bank a ? address bit [20:3] b8 la_adsc# output with pull up frame bank a address status control c1 la_clk output with pull up frame bank a clock input c9 la_we# output with pull up frame bank a write chip select for one layer sram application d12 la_we0# output with pull up frame bank a write chip select for lower layer of two bank sram application e12 la_we1# output with pull up frame bank a write chip select for upper bank of two layer sram application c8 la_oe# output with pull up frame bank a read chip select for one layer sram application zl50418 data sheet 127 zarlink semiconductor inc. a9 la_oe0# output with pull up frame bank a read chip select for lower layer of tw o layers sram application b9 la_oe1# output with pull up frame bank a read chip select for upper layer of two layers sram application f4, f5, g4, g5, h4, h5, j4, j5, k4, k5, l4, l5, m4, m5, n4, n5, g3, h1, h2, h3, j1, j2, j3, k1, k2, k3, l1, l2, l3, m1, m2, m3, u4, u5, v4, v5, w4, w5, y4, y5, aa4, aa5, ab4, ab5, ac4, ac5, ad4, ad5, w1, y1, y2, y3, aa1, aa2, aa3, ab1, ab2, ab3, ac1, ac2, ac3, ad1, ad2, ad3 lb_d[63:0] i/o-ts with pull up. frame bank b? data bit [63:0] n3, n2, n1, p3, p2, p1, r5, r4, r3, r2, r1, t5, t4, t3, t2, t1, w3, w2 lb_a[20:3] output frame bank b ? address bit [20:3] v1 lb_adsc# output with pull up frame bank b address status control g1 lb_clk output with pull up frame bank b clock input v3 lb_we# output with pull up frame bank b write chip select for one layer sram application p4 lb_we0# output with pull up frame bank b write chip select for lower layer of tw o layers sram application p5 lb_we1# output with pull up frame bank b write chip select for upper layer of two layers sram application v2 lb_oe# output with pull up frame bank b read chip select for one layer sram application u1 lb_oe0# output with pull up frame bank b read chip select for lower layer of tw o layers sram application u2 lb_oe1# output with pull up frame bank b read chip select for upper layer of two layers sram application fast ethernet access ports [15:0] rmii r28 m_mdc output mii management data clock ? (common for all mii ports [15:0]) p28 m_mdio i/o-ts with pull up mii management data i/o ? (common for all mii ports ?[15:0]) ball no(s) symbol i/o description zl50418 data sheet 128 zarlink semiconductor inc. r29 m_clki input reference input clock af21, aj19, af18, aj17, aj15, af15, aj13, af12, aj11, aj9, af9, aj7, af6, aj5, aj3, af1 m[15:0]_rxd[1] input with weak internal pull up resistors. ports [15:0] ? receive data bit [1] ae21, ah19, ah20, ah17, ah15, ae15, ah13, ae12, ah11, ah9, ae9, ah7, ae6, ah5, ah2, af2 m[15:0]_rxd[0] input with weak internal pull up resistors ports [15:0] ? receive data bit [0] ah21, af19, af17, ag17, ag15, af14, ag13, af11, ag11, ag9, af8, ag7, af5, ag5, ah3, af3 m[15:0]_crs_dv input with weak internal pull down resistors. ports [15:0] ? carrier sense and receive data valid ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1 m[15:0]_txen i/o- ts with pull up, slew ports [15:0] ? transmit enable strap option for rmii/gpsi ae18, ag18, ae16, ag16, ag14, ae13, ag12, ae10, ag10, ag8, ae7, ag6, ae4, ag4, ag3, ae3 m[15:0]_txd[1] output, slew ports [1 5:0] ? transmit data bit [1] ag19, ah18, af16, ah16, ah14, af13, ah12, af10, ah10, ah8, af7, ah6, af4, ah4, ag2, ae2 m[15:0]_txd[0] output, slew ports [1 5:0] ? transmit data bit [0] gmii/tbi gigabit ethernet access ports 0 & 1 y27, y26, aa26, aa25, ab26, ab25, ac26, ac25, ad26, ad25 m25_txd[9:0] output tran smit data bit [9:0] t28 m25_rx_dv input w/ pulldown receive data valid u28 m25_rx_er input w/ pullup receive error r25 m25_crs input w/ pulldown carrier sense u29 m25_col input w/ pullup collision detected t29 m25_rxclk input w/ pullup receive clock w27, y29, y28, y25, aa29, aa28, aa27, ab29, ab28, ab27 m25_rxd[9:0] input w/ pullup receive data bit [9:0] t26 m25_tx_en output w/ pullup transmit data enable r26 m25_tx_er output w/ pullup transmit error t25 m25_ txclk output gigabit transmit clock ball no(s) symbol i/o description zl50418 data sheet 129 zarlink semiconductor inc. p29 gref_clk0 input w/ pullu p gigabit reference clock k25, k26, m25, l26, m26, l25, n26, n25, p26, p25 m26_txd[9:0] output tran smit data bit [9:0] f28 m26_rx_dv input w/ pulldown receive data valid g28 m26_rx_er input w/ pullup receive error e25 m26_crs input w/ pulldown carrier sense g29 m26_col input w/ pullup collision detected f29 m26_rxclk input w/ pullup receive clock j27, k29, k29, k28, k27, l29, l28, l27, m29, m28, m27 m26_rxd[9:0] input w/ pullup receive data bit [9:0] f26 m26_tx_en output w/ pullup transmit data enable e26 m26_tx_er output w/ pullup transmit error f25 m26_ txclk output gigabit transmit clock n29 gref_clk1 input w/ pullu p gigabit reference clock led interface c29 led_clk/tstout 0 i/o- ts with pull up led seri al interface output clock d29 led_syn/tstout 1 i/o- ts with pull up led output data stream envelope e29 led_bit/tstout2 i/o- ts with pull up led serial data output stream b28 g1_rxtx#/tstou t3 i/o- ts with pull up led for gigabit port 1 (receive + transmit) c28 g1_dpcol#/tsto ut4 i/o- ts with pull up led for gigabit port 1 (full duplex + collision) d28 g1_link#/tstout 5 i/o- ts with pull up led for gigabit port 1 e28 g2_rxtx#/tstou t6 i/o- ts with pull up led for gigabit port 2 (receive + transmit) a27 g2_dpcol#/tsto ut7 i/o- ts with pull up led for gigabit port 2 (full duplex + collision) b27 g2_link#/tstout 8 i/o- ts with pull up led for gigabit port 2 c27 init_done/tstou t9 i/o- ts with pull up system start operation d27 init_start/tsto ut10 i/o- ts with pull up start initialization c26 checksum_ok/t stout11 i/o- ts with pull up eeprom read ok ball no(s) symbol i/o description zl50418 data sheet 130 zarlink semiconductor inc. d26 fcb_err/tstout 12 i/o- ts with pull up fcb memory self test fail d25 mct_err/tstout 13 i/o- ts with pull up mct memory self test fail d24 bist_in_prc/tst out14 i/o- ts with pull up processing memory self test e24 bist_done/tsto ut15 i/o- ts with pull up memory self test done trunk enable c22 trunk0 input w/ weak internal pull down resistors trunk port enable in unmanaged mode in managed mode doesn't care a21 trunk1 input w/ weak internal pull down resistors trunk port enable in unmanaged mode in managed mode doesn't care b24 trunk2 input w/ weak internal pull down resistors trunk port enable in unmanaged mode in managed mode doesn't care test facility u3, c10 t_mode0, t_mode1 i/o-ts test pins 00 ? test mode ? set mode upon reset, and provides nand tree test output during test mode 01 - reserved - do not use 10 - reserved - do not use 11 ? normal mode. use external pull up for normal mode f3 scan_en input with pull down scan enable 0 - normal mode (open) e27 scanmode input with pull down 1 ? enable test mode 0 - normal mode (open) system clock, power, and ground pins e1 sclk input system clock at 100 mhz k12, k13, k17,k18 m10, n10, m20, n20, u10, v10, u20, v20, y12, y13, y17, y18 vdd power +2.5 volt dc supply f13, f14, f15, f16, f17, n6, p6, r6, t6, u6, n24, p24, r24, t24, u24, ad13, ad14, ad15, ad16, ad17 vcc power +3.3 volt dc supply ball no(s) symbol i/o description zl50418 data sheet 131 zarlink semiconductor inc. m12, m13, m14, m15, m16, m17, m18, n12, n13, n14, n15, n16, n17, n18, p12, p13, p14, p15, p16, p17, p18, r12, r13, r14, r15, r16, r17, r18, t12, t13, t14, t15, t16, t17, t18, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v18, vss power ground ground f1 avcc analog power analog +2.5 volt dc supply d1 agnd analog ground analog ground misc d22 scancol input scans the co llision signal of home phy d23 scanclk input/ output clock for scanning home phy collision and link e23 scanlink input link up signal from home phy f2 resin# input reset input g2 resetout# output reset phy ac29, ae28, aj27, af27, aj25, af24, ah23, ae19, ac27, af29, ag27, af26, ag25, ag23, af23, ag21, ac28, af28, ah27, ae27, ah25, ae24, af22, af20, ad29, ag28, aj26, ae26, aj24, ae23, aj22, aj20, ad27, ah28, ag26, ae25, ag24, ae22, aj23, ag20, ad28, ag29, ah26, af25, ah24, ag22, ah22, ae17, g27, h29, h28, h27, j29, j28, u26, u25, v26, v25, w26, w25, g26, g25, h26, h25, j26, j25, u27, v29, v28, v27, w29, w28, b22, a22, c23, b23, a23, c24, e20, b25 reserved na reserved pins . leave unc onnected. bootstrap pins (default = pull up, 1= pull up 0= pull down) after reset tstout0 to tstou15 are used by the led interface. ball no(s) symbol i/o description zl50418 data sheet 132 zarlink semiconductor inc. c29 tstout0 default 1 giga link polarity 0 ? active low 1 ? active high d29 tstout1 default 1 rmii mac power saving enable 0 ? no power saving 1 ? power saving e29 tstout2 default 1 recommend disable (0) with pull-down giga half duplex support 0 - disable 1 - enable b28 tstout3 default 1 module detect enable 0 ? hot swap enable 1 ? hot swap disable c28 tstout4 reserved d28 tstout5 default 1 scan speed: ? sclk or sclk 0 ? ? sclk (hpna) 1 - sclk e28 tstout6 default 1 cpu port mode 0 - 8 bit bus mode 1 - 16 bit bus mode a27 tstout7 default 1 memory size 0 - 256 k x 32 or 256 k x 64 (4 m total) 1 - 128 k x 32 or 128 k x 64 (2 m total) b27 tstout8 default 1 eeprom installed 0 ? eeprom installed 1 ? eeprom not installed c27 tstout9 default 1 mct aging 0 ? mct aging disable 1 ? mct aging enable d27 tstout10 default 1 fcb aging 0 - fcb aging disable 1 ? fcb aging enable c26 tstout11 default 1 timeout reset 0 ? time out reset disable 1 ? time out reset enable. issue reset if any state machine did not go back to idle for 5sec. d26 tstout12 reserved d25 tstout13 default 1 fdb ram depth (1 or 2 layers) 0 ? 2 layer 1 ? 1 layer d24 tstout14 default 1 cpu installed 0 ? cpu installed 1 ? cpu not installed ball no(s) symbol i/o description zl50418 data sheet 133 zarlink semiconductor inc. notes: # =active low signal input = input signal in-st =input signal with schmitt-trigger output = output signal (tri-state driver) out-od = output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver e24 tstout15 default 1 sram test mode 0 ? enable test mode 1 ? normal operation t26, r26 g0_txen, g0_txer default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs f26, e26 g1_txen, g1_txer default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1, m[15:0]_txen default: rmii 0 ? gpsi 1 - rmii c21 p_d must be pulled-down reserved - must be pulled-down c19, b19, a19 oe_clk[2:0] default: 111 programmable delay for internal oe_clk from sclk input. the oe_clk is used for generating the oe0 and oe1 signals suggested value is 001. c20, b20, a20 la_clk[2:0] default: 111 programmable delay for la_clk and lb_clk from internal oe_clk. the la_clk and lb_clk delay from sclk is the sum of the delay programmed in here and the delay in p_d[15:13]. suggested value is 011. ball no(s) symbol i/o description zl50418 data sheet 134 zarlink semiconductor inc. 15.3 ball ? signal name in unmanaged mode ball no. signal name ball no. signal name ball no. signal name d20 la_d[63] d3 la_d[19] a9 la_oe0# b21 la_d[62] e3 la_d[18] b9 la_oe1# d19 la_d[61] d2 la_d[17] f4 lb_d[63] e19 la_d[60] e2 la_d[16] f5 lb_d[62] d18 la_d[59] a7 la_d[15] g4 lb_d[61] e18 la_d[58] b7 la_d[14] g5 lb_d[60] d17 la_d[57] a6 la_d[13] h4 lb_d[59] e17 la_d[56] b6 la_d[12] h5 lb_d[58] d16 la_d[55] c6 la_d[11] j4 lb_d[57] e16 la_d[54] a5 la_d[10] j5 lb_d[56] d15 la_d[53] b5 la_d[9] k4 lb_d[55] e15 la_d[52] c5 la_d[8] k5 lb_d[54] d14 la_d[51] a4 la_d[7] l4 lb_d[53] e14 la_d[50] b4 la_d[6] l5 lb_d[52] d13 la_d[49] c4 la_d[5] m4 lb_d[51] e13 la_d[48] a3 la_d[4] m5 lb_d[50] d21 la_d[47] b3 la_d[3] n4 lb_d[49] e21 la_d[46] c3 la_d[2] n5 lb_d[48] a18 la_d[45] b2 la_d[1] g3 lb_d[47] b18 la_d[44] c2 la_d[0] h1 lb_d[46] c18 la_d[43] c14 la_a[20] h2 lb_d[45] a17 la_d[42] a13 la_a[19] h3 lb_d[44] b17 la_d[41] b13 la_a[18] j1 lb_d[43] c17 la_d[40] c13 la_a[17] j2 lb_d[42] a16 la_d[39] a12 la_a[16] j3 lb_d[41] b16 la_d[38] b12 la_a[15] k1 lb_d[40] c16 la_d[37] c12 la_a[14] k2 lb_d[39] a15 la_d[36] a11 la_a[13] k3 lb_d[38] b15 la_d[35] b11 la_a[12] l1 lb_d[37] c15 la_d[34] c11 la_a[11] l2 lb_d[36] a14 la_d[33] d11 la_a[10] l3 lb_d[35] b14 la_d[32] e11 la_a[9] m1 lb_d[34] zl50418 data sheet 135 zarlink semiconductor inc. d9 la_d[31] a10 la_a[8] m2 lb_d[33] e9 la_d[30] b10 la_a[7] m3 lb_d[32] d8 la_d[29] d10 la_a[6] u4 lb_d[31] e8 la_d[28] e10 la_a[5] u5 lb_d[30] d7 la_d[27] a8 la_a[4] v4 lb_d[29] e7 la_d[26] c7 la_a[3] v5 lb_d[28] d6 la_d[25] b8 la_dsc# w4 lb_d[27] e6 la_d[24] c1 la_clk w5 lb_d[26] d5 la_d[23] c9 la_we# y4 lb_d[25] e5 la_d[22] d12 la_we0# y5 lb_d[24] d4 la_d[21] e12 la_we1# aa4 lb_d[23] e4 la_d[20] c8 la_oe# aa5 lb_d[22] ab4 lb_d[21] u2 lb_oe1# ah7 m[4]_rxd[0] ab5 lb_d[20] r28 mdc ae6 m[3]_rxd[0] ac4 lb_d[19] p28 md io ah5 m[2]_rxd[0] ac5 lb_d[18] r29 m_clk ah2 m[1]_rxd[0] ad4 lb_d[17] ac29 reserved af2 m[0]_rxd[0] ad5 lb_d[16] ae28 reserved ac27 reserved w1 lb_d[15] aj27 reserved af29 reserved y1 lb_d[14] af27 reserved ag27 reserved y2 lb_d[13] aj25 reserved af26 reserved y3 lb_d[12] af24 reserved ag25 reserved aa1 lb_d[11] ah23 reserved ag23 reserved aa2 lb_d[10] ae19 reserved af23 reserved aa3 lb_d[9] af21 m[15]_rxd[1] ag21 reserved ab1 lb_d[8] aj19 m[14]_rxd[1] ah21 m[15]_crs_dv ab2 lb_d[7] af18 m[13]_rxd[1] af19 m[14]_crs_dv ab3 lb_d[6] aj17 m[12]_rxd[1] af17 m[13]_crs_dv ac1 lb_d[5] aj15 m[11]_rxd[1] ag17 m[12]_crs_dv ac2 lb_d[4] af15 m[10]_rx d[1] ag15 m[11]_crs_dv ac3 lb_d[3] aj13 m[9]_rxd[1] af14 m[10]_crs_dv ad1 lb_d[2] af12 m[8]_r xd[1] ag13 m[9]_crs_dv ad2 lb_d[1] aj11 m[7]_r xd[1] af11 m[8]_crs_dv ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 136 zarlink semiconductor inc. ad3 lb_d[0] aj9 m[6]_rxd[1] ag11 m[7]_crs_dv n3 lb_a[20] af9 m[5]_rxd[1] ag9 m[6]_crs_dv n2 lb_a[19] aj7 m[4]_rxd[1] af8 m[5]_crs_dv n1 lb_a[18] af6 m[3]_rxd[1] ag7 m[4]_crs_dv p3 lb_a[17] aj5 m[2]_rx d[1] af5 m[3]_crs_dv p2 lb_a[16] aj3 m[1]_rx d[1] ag5 m[2]_crs_dv p1 lb_a[15] af1 m[0]_rx d[1] ah3 m[1]_crs_dv r5 lb_a[14] ac28 reser ved af3 m[0]_crs_dv r4 lb_a[13] af28 reserved ad29 reserved r3 lb_a[12] ah27 reserved ag28 reserved r2 lb_a[11] ae27 reserved aj26 reserved r1 lb_a[10] ah25 reserved ae26 reserved t5 lb_a[9] ae24 reserved aj24 reserved t4 lb_a[8] af22 reserved ae23 reserved t3 lb_a[7] af20 reserved aj22 reserved t2 lb_a[6] ae21 m[15]_rxd[0] aj20 reserved t1 lb_a[5] ah19 m[14]_rxd[0] ae20 m[15]_txen w3 lb_a[4] ah20 m[13]_rxd[0] aj18 m[14]_txen w2 lb_a[3] ah17 m[12]_rxd[0] aj21 m[13]_txen v1 lb_adsc# ah15 m[11]_ rxd[0] aj16 m[12]_txen g1 lb_clk ae15 m[10]_rxd[0] aj14 m[11]_txen v3 lb_we# ah13 m[9]_rxd[0] ae14 m[10]_txen p4 lb_we0# ae12 m[8]_rxd[0] aj12 m[9]_txen p5 lb_we1# ah11 m[7]_rxd[0] ae11 m[8]_txen v2 lb_oe# ah9 m[6]_rx d[0] aj10 m[7]_txen u1 lb_oe0# ae9 m[5]_r xd[0] aj8 m[6]_txen ae8 m[5]_txen ah8 m[6]_txd[0] g27 reserved aj6 m[4]_txen af7 m[5]_txd[0] h29 reserved ae5 m[3]_txen ah6 m[4]_txd[0] h28 reserved aj4 m[2]_txen af4 m[3]_txd[0] h27 reserved ag1 m[1]_txen ah4 m[2]_txd[0] j29 reserved ae1 m[0]_txen ag2 m[1]_txd[0] j28 reserved ad27 reserved ae2 m[0]_txd[0] j27 m26_rxd[9] ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 137 zarlink semiconductor inc. ah28 reserved u26 reserved k29 m26_rxd[8] ag26 reserved u25 reserved k28 m26_rxd[7] ae25 reserved v26 reserved k27 m26_rxd[6] ag24 reserved v25 reserved l29 m26_rxd[5] ae22 reserved w26 reserved l28 m26_rxd[4] aj23 reserved w25 reserved l27 m26_rxd[3] ag20 reserved y27 m25_txd[9] m29 m26_rxd[2] ae18 m[15]_txd[1] y26 m25_txd[8] m28 m26_rxd[1] ag18 m[14]_txd[1] aa26 m25_txd[7] m27 m26_rxd[0] ae16 m[13]_txd[1] aa25 m25_txd[6] g26 reserved ag16 m[12]_txd[1] ab26 m25_txd[5] g25 reserved ag14 m[11]_txd[1] ab25 m25_txd[4] h26 reserved ae13 m[10]_txd[1] ac26 m25_txd[3] h25 reserved ag12 m[9]_txd[1] ac25 m25_txd[2] j26 reserved ae10 m[8]_txd[1] ad26 m25_txd[1] j25 reserved ag10 m[7]_txd[1] ad25 m25_txd[0] k25 m26_txd[9] ag8 m[6]_txd[1] u27 reserved k26 m26_txd[8] ae7 m[5]_txd[1] v29 reserved m25 m26_txd[7] ag6 m[4]_txd[1] v28 reserved l26 m26_txd[6] ae4 m[3]_txd[1] v27 reserved m26 m26_txd[5] ag4 m[2]_txd[1] w29 reserved l25 m26_txd[4] ag3 m[1]_txd[1] w28 reserved n26 m26_txd[3] ae3 m[0]_txd[1] w27 m25_rxd[9] n25 m26_txd[2] ad28 reserved y29 m25_rxd[8] p26 m26_txd[1] ag29 reserved y28 m25_rxd[7] p25 m26_txd[0] ah26 reserved y25 m25_rxd[6] f28 m26_rx_dv af25 reserved aa29 m25_rxd[5] g28 m26_rx_er ah24 reserved aa28 m25_rxd[4] e25 m26_crs ag22 reserved aa27 m25_rxd[3] g29 m26_col ah22 reserved ab29 m25_rxd[2] f29 m26_rxclk ae17 reserved ab28 m25_rxd[1] f26 m26_tx_en ag19 m[15]_txd[0] ab27 m25_rxd[0] e26 m26_tx_er ah18 m[14]_txd[0] r26 m25_tx_er f25 m26_txclk ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 138 zarlink semiconductor inc. af16 m[13]_txd[0] t25 m25_txclk e24 bist_done/tstout[15] ah16 m[12]_txd[0] t26 m25_tx_en d24 bist_in_prc/tst0ut[14] ah14 m[11]_txd[0] t28 m25_rx_dv d25 mct_err/tstout[13] af13 m[10]_txd[0] u28 m25_rx_er d26 fcb_err/tstout[12] ah12 m[9]_txd[0] r25 m25_crs c26 checksum_ok/tstout[11 ] af10 m[8]_txd[0] u29 m25_col d27 init_start/tstout[10] ah10 m[7]_txd[0] t29 m25_rxcl k c27 init_done/tstout[9] b27 g2_link#/tstout[8] u18 vss n12 vss a27 g2_dpcol#/tstout[7 ] v12 vss n13 vss e28 g2_rxtx#/tstout[6] v13 vss k17 vdd d28 g1_link#/tstout[5] v14 vss k18 vdd c28 g1_dpcol#/tstout[4 ] v15 vss m10 vdd b28 g1_rxtx#/tstout[3] v16 vss n10 vdd e29 led_bit/tstout[2] v17 vss m20 vdd d29 led_syn/tstout[1] v18 vss n20 vdd c29 led_clk/tstout[0] n14 vss u10 vdd n29 gref_clk1 n15 vss v10 vdd p29 gref_clk0 n16 vss u20 vdd f3 scan_en n17 vss v20 vdd e1 sclk n18 vss y12 vdd u3 t_mode0 p12 vss y13 vdd c10 t_mode1 p13 vss y17 vdd b24 trunk2 p14 vss y18 vdd a21 trunk1 p15 vss k12 vdd c22 trunk0 p16 vss k13 vdd a26 strobe c19 oe_clk2 m16 vss b26 d0 b19 oe_clk1 m17 vss c25 autofd a19 oe_clk0 m18 vss a24 scl r13 vss f16 vcc a25 sda r14 vss f17 vcc f1 avcc r15 vss n6 vcc ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 139 zarlink semiconductor inc. d1 agnd r16 vss p6 vcc d22 scancol r17 vss r6 vcc e23 scanlink r18 vss t6 vcc e27 scanmode t12 vss u6 vcc n28 t13 vss n24 vcc n27 t14 vss p24 vcc f2 resin# t15 vss r24 vcc g2 resetout# t16 vss t24 vcc b22 reserved t17 vss u24 vcc a22 reserved t18 vss ad13 vcc c23 reserved u12 vss ad14 vcc b23 reserved u13 vss ad15 vcc a23 reserved u14 vss ad16 vcc c24 reserved u15 vss ad17 vcc d23 scanclk u16 vss f13 vcc t27 m25_mtxclk u17 vss f14 vcc f27 m26_mtxclk m12 vss f15 vcc c20 la_clk2 m13 vss b20 la_clk1 m14 vss a20 la_clk0 m15 vss c21 p_d p17 vss e20 reserved p18 vss b25 reserved r12 vss ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 140 zarlink semiconductor inc. 15.4 ball ? signal name in managed mode ball no. signal name ball no. signal name ball no. signal name d20 la_d[63] d3 la_d[19] a9 la_oe0# b21 la_d[62] e3 la_d[18] b9 la_oe1# d19 la_d[61] d2 la_d[17] f4 lb_d[63] e19 la_d[60] e2 la_d[16] f5 lb_d[62] d18 la_d[59] a7 la_d[15] g4 lb_d[61] e18 la_d[58] b7 la_d[14] g5 lb_d[60] d17 la_d[57] a6 la_d[13] h4 lb_d[59] e17 la_d[56] b6 la_d[12] h5 lb_d[58] d16 la_d[55] c6 la_d[11] j4 lb_d[57] e16 la_d[54] a5 la_d[10] j5 lb_d[56] d15 la_d[53] b5 la_d[9] k4 lb_d[55] e15 la_d[52] c5 la_d[8] k5 lb_d[54] d14 la_d[51] a4 la_d[7] l4 lb_d[53] e14 la_d[50] b4 la_d[6] l5 lb_d[52] d13 la_d[49] c4 la_d[5] m4 lb_d[51] e13 la_d[48] a3 la_d[4] m5 lb_d[50] d21 la_d[47] b3 la_d[3] n4 lb_d[49] e21 la_d[46] c3 la_d[2] n5 lb_d[48] a18 la_d[45] b2 la_d[1] g3 lb_d[47] b18 la_d[44] c2 la_d[0] h1 lb_d[46] c18 la_d[43] c14 la_a[20] h2 lb_d[45] a17 la_d[42] a13 la_a[19] h3 lb_d[44] b17 la_d[41] b13 la_a[18] j1 lb_d[43] c17 la_d[40] c13 la_a[17] j2 lb_d[42] a16 la_d[39] a12 la_a[16] j3 lb_d[41] b16 la_d[38] b12 la_a[15] k1 lb_d[40] c16 la_d[37] c12 la_a[14] k2 lb_d[39] a15 la_d[36] a11 la_a[13] k3 lb_d[38] b15 la_d[35] b11 la_a[12] l1 lb_d[37] c15 la_d[34] c11 la_a[11] l2 lb_d[36] a14 la_d[33] d11 la_a[10] l3 lb_d[35] zl50418 data sheet 141 zarlink semiconductor inc. b14 la_d[32] e11 la_a[9] m1 lb_d[34] d9 la_d[31] a10 la_a[8] m2 lb_d[33] e9 la_d[30] b10 la_a[7] m3 lb_d[32] d8 la_d[29] d10 la_a[6] u4 lb_d[31] e8 la_d[28] e10 la_a[5] u5 lb_d[30] d7 la_d[27] a8 la_a[4] v4 lb_d[29] e7 la_d[26] c7 la_a[3] v5 lb_d[28] d6 la_d[25] b8 la_dsc# w4 lb_d[27] e6 la_d[24] c1 la_clk w5 lb_d[26] d5 la_d[23] c9 la_we# y4 lb_d[25] e5 la_d[22] d12 la_we0# y5 lb_d[24] d4 la_d[21] e12 la_we1# aa4 lb_d[23] e4 la_d[20] c8 la_oe# aa5 lb_d[22] ab4 lb_d[21] u2 lb_oe1# ah7 m[4]_rxd[0] ab5 lb_d[20] r28 mdc ae6 m[3]_rxd[0] ac4 lb_d[19] p28 mdio ah5 m[2]_rxd[0] ac5 lb_d[18] r29 m_clk ah2 m[1]_rxd[0] ad4 lb_d[17] ac29 reserved af2 m[0]_rxd[0] ad5 lb_d[16] ae28 reserved ac27 reserved w1 lb_d[15] aj27 reserved af29 reserved y1 lb_d[14] af27 reserved ag27 reserved y2 lb_d[13] aj25 reserved af26 reserved y3 lb_d[12] af24 reserved ag25 reserved aa1 lb_d[11] ah23 reserved ag23 reserved aa2 lb_d[10] ae19 reserved af23 reserved aa3 lb_d[9] af21 m[15]_rxd[1] ag21 reserved ab1 lb_d[8] aj19 m[14]_rxd[1] ah21 m[15]_crs_dv ab2 lb_d[7] af18 m[13]_rxd[1] af19 m[14]_crs_dv ab3 lb_d[6] aj17 m[12]_rxd[1] af17 m[13]_crs_dv ac1 lb_d[5] aj15 m[11]_rxd[1] ag17 m[12]_crs_dv ac2 lb_d[4] af15 m[10]_rxd [1] ag15 m[11]_crs_dv ac3 lb_d[3] aj13 m[9]_rxd[1] af14 m[10]_crs_dv ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 142 zarlink semiconductor inc. ad1 lb_d[2] af12 m[8]_rxd[1] ag13 m[9]_crs_dv ad2 lb_d[1] aj11 m[7]_rxd[1] af11 m[8]_crs_dv ad3 lb_d[0] aj9 m[6]_rxd[1] ag11 m[7]_crs_dv n3 lb_a[20] af9 m[5]_rxd[1] ag9 m[6]_crs_dv n2 lb_a[19] aj7 m[4]_rxd[1] af8 m[5]_crs_dv n1 lb_a[18] af6 m[3]_rxd[1] ag7 m[4]_crs_dv p3 lb_a[17] aj5 m[2]_rxd[1] af5 m[3]_crs_dv p2 lb_a[16] aj3 m[1]_rxd[1] ag5 m[2]_crs_dv p1 lb_a[15] af1 m[0]_rxd[1] ah3 m[1]_crs_dv r5 lb_a[14] ac28 reserved af3 m[0]_crs_dv r4 lb_a[13] af28 reserved ad29 reserved r3 lb_a[12] ah27 reserved ag28 reserved r2 lb_a[11] ae27 reserved aj26 reserved r1 lb_a[10] ah25 reserved ae26 reserved t5 lb_a[9] ae24 reserved aj24 reserved t4 lb_a[8] af22 reserved ae23 reserved t3 lb_a[7] af20 reserved aj22 reserved t2 lb_a[6] ae21 m[15]_rxd[0] aj20 reserved t1 lb_a[5] ah19 m[14]_rxd[0] ae20 m[15]_txen w3 lb_a[4] ah20 m[13]_rxd[0] aj18 m[14]_txen w2 lb_a[3] ah17 m[12]_rxd[0] aj21 m[13]_txen v1 lb_adsc# ah15 m[11]_rxd[0] aj16 m[12]_txen g1 lb_clk ae15 m[10]_rxd[0] aj14 m[11]_txen v3 lb_we# ah13 m[9]_rxd[0] ae14 m[10]_txen p4 lb_we0# ae12 m[8]_rxd[0] aj12 m[9]_txen p5 lb_we1# ah11 m[7]_rxd[0] ae11 m[8]_txen v2 lb_oe# ah9 m[6]_rxd[0] aj10 m[7]_txen u1 lb_oe0# ae9 m[5]_rxd[0] aj8 m[6]_txen ae8 m[5]_txen ah8 m[6]_txd[0] g27 reserved aj6 m[4]_txen af7 m[5]_txd[0] h29 reserved ae5 m[3]_txen ah6 m[4]_txd[0] h28 reserved aj4 m[2]_txen af4 m[3]_txd[0] h27 reserved ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 143 zarlink semiconductor inc. ag1 m[1]_txen ah4 m[2]_txd[0] j29 reserved ae1 m[0]_txen ag2 m[1]_txd[0] j28 reserved ad27 reserved ae2 m[0]_txd[0] j27 m26_rxd[9] ah28 reserved u26 reserved k29 m26_rxd[8] ag26 reserved u25 reserved k28 m26_rxd[7] ae25 reserved v26 reserved k27 m26_rxd[6] ag24 reserved v25 reserved l29 m26_rxd[5] ae22 reserved w26 reserved l28 m26_rxd[4] aj23 reserved w25 reserved l27 m26_rxd[3] ag20 reserved y27 m25_txd[9] m29 m26_rxd[2] ae18 m[15]_txd[1] y26 m25_txd[8] m28 m26_rxd[1] ag18 m[14]_txd[1] aa26 m25_txd[7] m27 m26_rxd[0] ae16 m[13]_txd[1] aa25 m25_txd[6] g26 reserved ag16 m[12]_txd[1] ab26 m25_txd[5] g25 reserved ag14 m[11]_txd[1] ab25 m25_txd[4] h26 reserved ae13 m[10]_txd[1] ac26 m25_txd[3] h25 reserved ag12 m[9]_txd[1] ac25 m25_txd[2] j26 reserved ae10 m[8]_txd[1] ad26 m25_txd[1] j25 reserved ag10 m[7]_txd[1] ad25 m25_txd[0] k25 m26_txd[9] ag8 m[6]_txd[1] u27 reserved k26 m26_txd[8] ae7 m[5]_txd[1] v29 reserved m25 m26_txd[7] ag6 m[4]_txd[1] v28 reserved l26 m26_txd[6] ae4 m[3]_txd[1] v27 reserved m26 m26_txd[5] ag4 m[2]_txd[1] w29 reserved l25 m26_txd[4] ag3 m[1]_txd[1] w28 re served n26 m26_txd[3] ae3 m[0]_txd[1] w27 m25_rxd[9] n25 m26_txd[2] ad28 reserved y29 m25_rxd[8] p26 m26_txd[1] ag29 reserved y28 m25_rxd[7] p25 m26_txd[0] ah26 reserved y25 m25_rxd[6] f28 m26_rx_dv af25 reserved aa29 m25 _rxd[5] g28 m26_rx_er ah24 reserved aa28 m25_rxd[4] e25 m26_crs ag22 reserved aa27 m25_rxd[3] g29 m26_col ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 144 zarlink semiconductor inc. ah22 reserved ab29 m25 _rxd[2] f29 m26_rxclk ae17 reserved ab28 m25_r xd[1] f26 m26_tx_en ag19 m[15]_txd[0] ab27 m25_rxd[0] e26 m26_tx_er ah18 m[14]_txd[0] r26 m25_tx_er f25 m26_txclk af16 m[13]_txd[0] t25 m25_txclk e24 bist_done/tstout[15] ah16 m[12]_txd[0] t26 m25_tx_en d24 bist_in_prc/tst0ut[14] ah14 m[11]_txd[0] t28 m25_rx_dv d25 mct_err/tstout[13] af13 m[10]_txd[0] u28 m25_rx_er d26 fcb_err/tstout[12] ah12 m[9]_txd[0] r25 m25_crs c26 checksum_ok/tstout[ 11] af10 m[8]_txd[0] u29 m25_col d27 init_start/tstout[10] ah10 m[7]_txd[0] t29 m25_rxclk c27 init_done/tstout[9] b27 g2_link#/tstout[8] u18 vss n12 vss a27 g2_dpcol#/tstout [7] v12 vss n13 vss e28 g2_rxtx#/tstout[6 ] v13 vss k17 vdd d28 g1_link#/tstout[5] v14 vss k18 vdd c28 g1_dpcol#/tstout [4] v15 vss m10 vdd b28 g1_rxtx#/tstout[3 ] v16 vss n10 vdd e29 led_bit/tstout[2] v17 vss m20 vdd d29 led_syn/tstou t[1] v18 vss n20 vdd c29 led_clk/tstout[0] n14 vss u10 vdd n29 gref_clk1 n15 vss v10 vdd p29 gref_clk0 c19 p_data15 u20 vdd f3 scan_en b19 p_data14 v20 vdd e1 sclk a19 p_data13 y12 vdd u3 t_mode0 p12 vss y13 vdd c10 t_mode1 p13 vss y17 vdd b24 p_data6 p14 vss y18 vdd a21 p_data7 p15 vss k12 vdd c22 p_a2 p16 vss k13 vdd ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 145 zarlink semiconductor inc. a26 p_we n16 vss m16 vss b26 p_rd n17 vss m17 vss c25 p_cs n18 vss m18 vss a24 p_a1 r13 vss f16 vcc a25 p_a0 r14 vss f17 vcc f1 avcc r15 vss n6 vcc d1 agnd r16 vss p6 vcc d22 scancol r17 vss r6 vcc e23 scanlink r18 vss t6 vcc e27 scanmode t12 vss u6 vcc n28 t13 vss n24 vcc n27 t14 vss p24 vcc f2 resin# t15 vss r24 vcc g2 resetout# t16 vss t24 vcc b22 p_data5 t17 vss u24 vcc a22 p_data4 t18 vss ad13 vcc c23 p_data3 u12 vss ad14 vcc b23 p_data2 u13 vss ad15 vcc a23 p_data1 u14 vss ad16 vcc c24 p_data0 u15 vss ad17 vcc d23 scanclk u16 vss f13 vcc t27 m25_mtxclk u17 vss f14 vcc f27 m26_mtxclk m12 vss f15 vcc c20 p_data12 m13 vss b20 p_data11 m14 vss a20 p_data10 m15 vss c21 p_data9 p17 vss e20 p_data8 p18 vss b25 p_int r12 vss ball no. signal name ball no. signal name ball no. signal name zl50418 data sheet 146 zarlink semiconductor inc. 15.5 ac/dc timing 15.5.1 absolute maximum ratings storage temperature -65 c to +150 c operating temperature -40 c to +85 c maximum junction temperature +125 c supply voltage vcc with respect to v ss +3.0 v to +3.6 v supply voltage vdd with respect to v ss +2.38 v to +2.75 v voltage on input pins -0.5 v to (vcc + 3.3 v) caution: stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods may affect device reliability. functiona lity at or above these limits is not implied. 15.5.2 dc electrical characteristics vcc = 3.0 v to 3.6 v (3.3v +/- 10%)t ambient = -40c to +85 c vdd = 2.5 v +10% - 5% 15.5.3 recommended operating conditions symbol parameter description min. typ. max. unit f osc frequency of operation (-50) 100 mhz i cc supply current ? @ 100 mhz (vcc=3.3 v) 350 ma i dd supply current ? @ 100 mhz (vdd=2.5 v) 1400 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5 v tolerant) 2.0 vcc + 2.0 v v il-ttl input low voltage (ttl 5 v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vcc) (all pins except those with internal pull-up/pull-down resistors) 10 a iol output leakage current (0.1 v < vout < vcc) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 11.2 c/w ja thermal resistance with 1 m/s air flow 10.2 c/w ja thermal resistance with 2 m/s air flow 8.9 c/w jc thermal resistance between junction and case 3.1 c/w zl50418 data sheet 147 zarlink semiconductor inc. 15.5.4 typical reset & bootstrap timing diagram figure 18 - typical reset & bootstrap timing diagram jb thermal resistance between junction and board 6.6 c/w symbol parameter min. typ. note: r1 delay until resetout# is tri-st ated 10 ns resetout# state is then determined by the external pull-up/down resistor r2 bootstrap stabilization 1 s10 s bootstrap pins sampled on rising edge of resin# 1 1. the tstout[8:0] pins will switch over to the led inte rface functionality in 3 sclk cycles after resin# goes high r3 resetout# assertion 2 ms table 16 - reset & bootstrap timing symbol parameter description min. typ. max. unit resetout# tri-stated resin# r1 r2 r3 bootstrap pins inputs outputs outputs zl50418 data sheet 148 zarlink semiconductor inc. 15.5.5 typical cpu timing diagram for a cpu write cycle figure 19 - typical cpu timing diagram for a cpu write cycle table 17 - write cycle description (sclk=100 mh z) refer to figure 19 write cycle symbol min. max. write set up time t ws 10 write active time t wa 20 at least 2 sclk write hold time t wh 2 write recovery time t wr 30 at least 3 sclk data set up time t ds 10 data hold time t dh 2 p_cs# p_we# data to vtx2600 p_addr t wr hold time addr0 t ws t wa at least 2 sclks set up time data 1 data 0 recovery time addr1 t wh t ws t wa at least 2 sclks t wh t dh t dh t ds t ds data to zl5041x zl50418 data sheet 149 zarlink semiconductor inc. 15.5.6 typical cpu timing diagram for a cpu read cycle figure 20 - typical cpu timing diagram for a cpu read cycle table 18 - read cycle description (sclk=100 mh z) refer to figure 20 read cycle symbol min. max. read set up time t rs 10 read active time t ra 20 at least 2 sclk read hold time t rh 2 read recovery time t rr 30 at least 3 sclk data valid time t dv 10 data invalid time t di 6 p_cs# p_rd# data to cpu p_addr t rr recovery time 2ns invalid time addr0 t rs t dv t ra at least 2 sclks valid time data 1 data 0 at least 3 sclks t di addr1 t rh t rs t ra at least 2 sclks t rh t di t dv zl50418 data sheet 150 zarlink semiconductor inc. 15.6 local frame buff er sbram memory interface 15.6.1 local sbram memory interface figure 21 - local memory interface ? input setup and hold timing figure 22 - local memory interface - output valid delay timing l1 l2 la_clk la_d[63:0] l3-min l3-max l4-min l4-max l6-min l6-max l7-min l7-max l8-min l8-max la_clk la_d[63:0] la_a[20:3] la_adsc# la_we[1:0]# #### la_oe[1:0]# l9-min l9-max la_we# l10-min l10-max la_oe# zl50418 data sheet 151 zarlink semiconductor inc. 15.7 local switch data base sbram memory interface 15.7.1 local sbram memory interface figure 23 - local memory interface ? input setup and hold timing symbol parameter -100 mhz note min. (ns) max. (ns) l1 la_d[63:0] input set-up time 4 l2 la_d[63:0] input hold time 1.5 l3 la_d[63:0] output valid delay 1.5 7 c l = 25 pf l4 la_a[20:3] output valid delay 2 7 c l = 30 pf l6 la_adsc# output valid delay 1 7 c l = 30 pf l7 la_we[1:0]#output valid delay 1 7 c l = 25 pf l8 la_oe[1:0]# output valid delay -1 1 c l = 25 pf l9 la_we# output valid delay 1 7 c l = 25 pf l10 la_oe# output valid delay 1 5 c l = 25 pf table 19 - ac characteristics ? local frame buffer sbram memory interface l1 l2 lb_clk lb_d[63:0] zl50418 data sheet 152 zarlink semiconductor inc. figure 24 - local memory interface - output valid delay timing symbol parameter -100 mhz note min. (ns) max. (ns) l1 lb_d[63:0] input set-up time 4 l2 lb_d[63:0] input hold time 1.5 l3 lb_d[63:0] output valid delay 1.5 7 c l = 25 pf l4 lb_a[20:3] output valid delay 2 7 c l = 30 pf l6 lb_adsc# output valid delay 1 7 c l = 30 pf l8 lb_we[1:0]#output valid delay 1 7 c l = 25 pf l9 lb_oe[1:0]# output valid delay -1 1 c l = 25 pf l10 lb_we# output valid delay 1 7 c l = 25 pf l11 lb_oe# output valid delay 1 5 c l = 25 pf table 20 - ac characteristics ? local switch database sbram memory interface l3-min l3-max l4-min l4-max l6-min l6-max l8-min l8-max l9-min l9-max l10-min l10-max lb_clk lb_d[31:0] lb_a[21:2] lb_adsc# lb_we[1:0]# lb_oe[1:0]# lb_we# l11-min l11-max lb_oe# zl50418 data sheet 153 zarlink semiconductor inc. 15.8 ac characteristics 15.8.1 reduced media independent interface figure 25 - ac characteristics ? reduced media independent interface figure 26 - ac characteristics ? reduced media independent interface symbol parameter -50 mhz note min. (ns) max. (ns) m2 m[15:0]_rxd[1:0] input setup time 4 m3 m[15:0]_rxd[1:0] input hold time 1 m4 m[15:0]_crs_dv input setup time 4 m5 m[15:0]_crs_dv input hold time 1 m6 m[15:0]_txen output delay time 2 11 c l = 20 pf m7 m[15:0]_txd[1:0] output delay time 2 11 c l = 20 pf table 21 - ac characteristics ? reduced media independent interface m6-min m6-max m7-min m7-max m_clki m[23:0]_txen m[23:0] _txd[1:0] 15 1 5 m2 m_clki m[23:0]_rxd m[23:0]_crs_dv m3 m4 m5 15 15 zl50418 data sheet 154 zarlink semiconductor inc. 15.8.2 gigabit media independent interface - port a figure 27 - ac characteristics- gmii figure 28 - ac characteristics ? gi gabit media independent interface symbol parameter -125 mhz note min. (ns) max. (ns) g1 m[25]_rxd[7:0] input setup times 2 g2 m[25]_rxd[7:0] input hold times 1 g3 m[25]_rx_dv input setup times 2 g4 m[25]_rx_dv input hold times 1 g5 m[25]_rx_er input setup times 2 g6 m[25]_rx_er input hold times 1 g7 m[25]_crs input setup times 2 g8 m[25]_crs input hold times 1 g12 m[25]_txd[7:0] output delay times 1 6 c l = 20 pf g13 m[25]_tx_en output delay times 1 6.5 c l = 20 pf g14 m[25]_tx_er output delay times 1 6 c l = 20 pf table 22 - ac characteristics ? gigabit media independent interface g12-min g12-max g13-min g13-max g14-min g14-max m25_txclk m25_txd [7:0] m25_tx_en] m25_tx_er m25_rxclk g1 g2 m25_rxd[7:0] g3 g4 m25_rx_dv g5 g6 m25_rx_er g7 g8 m25 _ rx _ crs zl50418 data sheet 155 zarlink semiconductor inc. 15.8.3 ten bit interface - port a figure 29 - gigabit tbi interface transmit timing figure 30 - gigabit tbi interface receive timing symbol parameter min. (ns) max. (ns) note t1 m25_txd[9:0] output delay time 1 6 c l = 20 pf table 23 - output delay timing symbol parameter min. (ns) max. (ns) note t2 m25_rxd[9:0] input setup time 3 t3 m25_rxd[9:0] input hold time 3 table 24 - input setup timing m25_txclk m25_txd [9:0] timin timax m25_rxclk m25_col t2 m25_rxd[9:0] t3 t2 t3 zl50418 data sheet 156 zarlink semiconductor inc. 15.8.4 gigabit media independent interface - port b figure 31 - ac characteristics- gmii figure 32 - ac characteristics ? gi gabit media independent interface symbol parameter -125 mhz note min. (ns) max. (ns) g1 m[26]_rxd[7:0] input setup times 2 g2 m[26]_rxd[7:0] input hold times 1 g3 m[26]_rx_dv input setup times 2 g4 m[26]_rx_dv input hold times 1 g5 m[26]_rx_er input setup times 2 g6 m[26]_rx_er input hold times 1 g7 m[26]_crs input setup times 2 g8 m[26]_crs input hold times 1 g12 m[26]_txd[7:0] ou tput delay times 1 6 c l = 20 pf table 25 - ac characteristics ? gigabit media independent interface g12-min g12-max g13-min g13-max g14-min g14-max m26_txclk m26_txd [7:0] m26_tx_en] m26_tx_er m26_rxclk g1 g2 m26_rxd[7:0] g3 g4 m26_rx_dv g5 g6 m26_rx_er g7 g8 m26 _ rx _ crs zl50418 data sheet 157 zarlink semiconductor inc. 15.8.5 ten bit interface - port b figure 33 - gigabit tbi interface transmit timing figure 34 - gigabit tbi interface timing g13 m[26]_tx_en output delay times 1 6.5 c l = 20 pf g14 m[26]_tx_er output delay times 1 6 c l = 20 pf symbol parameter min. (ns) max. (ns) note t1 m26_txd[9:0] output delay time 1 6 c l = 20 pf table 26 - output delay timing symbol parameter min. (ns) max. (ns) note t2 m26_rxd[9:0] input setup time 3 t3 m26_rxd[9:0] input hold time 3 table 27 - input setup timing symbol parameter -125 mhz note min. (ns) max. (ns) table 25 - ac characteristics ? gigabit media independent interface (continued) m26_txclk m26_txd [9:0] timin timax m26_rxclk m26_col t2 m26_rxd[9:0] t3 t2 t3 zl50418 data sheet 158 zarlink semiconductor inc. 15.8.6 led interface figure 35 - ac characteristics ? led interface 15.8.7 scanlink s cancol output delay timing figure 36 - scanlink scancol output delay timing figure 37 - scanlink, scancol setup timing variable freq. symbol parameter min. (ns) max. (ns) note le5 led_syn output valid delay -1 7 c l = 30 pf le6 led_bit output valid delay -1 7 c l = 30 pf table 28 - ac characteristics ? led interface le5-min le5-max le6-min le6-max led_clk led_syn led_bit c5-min c5-max c7-min c7-max scanclk scanlink scancol scanclk c1 c2 scanlink c3 c4 scancol zl50418 data sheet 159 zarlink semiconductor inc. 15.8.8 mdio input setup and hold timing figure 38 - mdio input setup and hold timing figure 39 - mdio output delay timing -25 mhz symbol parameter min. (ns) max. (ns) note c1 scanlink input set-up time 20 c2 scanlink input hold time 2 c3 scancol input setup time 20 c4 scancol input hold time 1 c5 scanlink output valid delay 0 10 c l = 30 pf c7 scancol output valid delay 0 10 c l = 30 pf table 29 - scanlink, scancol timing mdc d1 d2 mdio d3-min d3-max mdc mdio zl50418 data sheet 160 zarlink semiconductor inc. 15.8.9 i 2 c input setup timing figure 40 - i 2 c input setup timing figure 41 - i 2 c output delay timing 1mhz symbol parameter min. (ns) max. (ns) note d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50 pf table 30 - mdio timing 50 khz symbol parameter min. (ns) max. (ns) note s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 4 usec 6 usec c l = 30 pf * open drain output. low to high transistor is controlled by exte rnal pullup resistor. table 31 - i 2 c timing s1 s2 scl sda s3-min s3-max scl sda zl50418 data sheet 161 zarlink semiconductor inc. 15.8.10 serial interface setup timing figure 42 - serial interface setup timing figure 43 - serial interface output delay timing symbol parameter min. (ns) max. (ns) note d1 d0 setup time 20 d2 d0 hold time 3 s d3 autofd output delay time 1 50 c l = 100 pf d4 strobe low time 5 s d5 strobe high time 5 s table 32 - serial interface timing strobe d1 d2 d0 d1 d2 d4 d5 d3-min d3-max strobe autofd apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 2.20 e e b e1 dimension d d1 a2 a1 a 1.27 553 max 0.70 2.46 1.17 ref 0.50 min 3. seating plane is defined by the spherical crowns of the solder balls. 1. controlling dimensions are in mm 2. dimension "b" is measured at the maximum solder ball diameter 4. n is the number of solder balls 5. not to scale. note: 0.60 0.90 37.30 37.70 34.50 ref 37.30 37.70 34.50 ref e1 d1 d e e b a2 6. substrate thickness is 0.56 mm www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
Price & Availability of ZL50418GKC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |